Patents by Inventor Sin-ichi Sinoda

Sin-ichi Sinoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Information processor and information processing system utilizing interface for synchronizing clock signal
    Patent number: 7111187
    Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: September 19, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
  • Information processor and information processing system utilizing interface for synchronizing clock signal
    Publication number: 20040093532
    Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.
    Type: Application
    Filed: November 6, 2003
    Publication date: May 13, 2004
    Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-Ichi Sinoda
  • Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
    Patent number: 6675311
    Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1, And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K1.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: January 6, 2004
    Assignee: HItachi, Ltd.
    Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
  • Information processor and information processing system utilizing interface for synchronizing clock signal
    Publication number: 20020059538
    Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1. and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.
    Type: Application
    Filed: December 6, 2001
    Publication date: May 16, 2002
    Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-Ichi Sinoda
  • Information processor and information processing system utilizing clock signal
    Patent number: 5974560
    Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: October 26, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
  • Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
    Patent number: 5640547
    Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: June 17, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
  • Information processor and information processing system utilizing clock signal
    Patent number: 5542083
    Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controllled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: July 30, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
  • Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
    Patent number: 5506982
    Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: April 9, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
  • Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
    Patent number: 5388249
    Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
    Type: Grant
    Filed: April 22, 1992
    Date of Patent: February 7, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
  • Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
    Patent number: 5133064
    Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
    Type: Grant
    Filed: April 22, 1988
    Date of Patent: July 21, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda