Patents by Inventor Sin-Jie Wang

Sin-Jie Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240427935
    Abstract: The present disclosure provides a method and an electronic apparatus for masking data on an electronic document. The method is performed by the electronic apparatus and includes: displaying the electronic document on a user interface; causing at least one analysis module to perform at least one analysis on the electronic document and a plurality of strings of the electronic document and output a first string among the plurality of strings and first position information associated with the first string according to a result of the at least one analysis; obtaining the first string and the first position information from the at least one analysis module; and generating, based on the first position information and the first string, a first masking object to mask the first string on the electronic document.
    Type: Application
    Filed: June 21, 2024
    Publication date: December 26, 2024
    Inventors: KANG-HUA HE, Yu-Chi Chen, Chia-Ting Lee, Wen-Wei Lin, Ching-Yi Chiang, Hsin-Yu Huang, Chun-Chin Su, Po-Chou Su, Sin-Jie Wang, Tso-Kuan Lee, Kai-Lin Shih
  • Patent number: 11687757
    Abstract: An integrated circuit, a wireless communication card and a wiring structure of an identification mark are provided. The integrated circuit includes a power supply wiring, a ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring that overlap each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: June 27, 2023
    Assignee: Au Optronics Corporation
    Inventors: Shyh-Bin Kuo, Hsiang-Chi Cheng, Sin-Jie Wang, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsing Hung
  • Patent number: 11610921
    Abstract: A chip is provided. The chip includes a flexible substrate, a plurality of thin-film transistors, a redistribution layer, a first power rail layer, and a second power rail layer. The plurality of thin-film transistors are disposed on the flexible substrate. The redistribution layer is disposed above the plurality of thin-film transistors. The first power rail layer is disposed above the redistribution layer. The first power rail layer provides a first voltage to the plurality of thin-film transistors. The second power rail layer is disposed above the first power rail layer. The second power rail layer provides a second voltage to the plurality of thin-film transistors, wherein the second power rail layer is disposed in a grid shape.
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: March 21, 2023
    Assignee: Au Optronics Corporation
    Inventors: Hsiang-Chi Cheng, Yi-Cheng Lai, Sin-Jie Wang, Shyh-Bin Kuo, Kuo-Hsiang Chen, Yu-Chih Wang, Chung-Hung Chen
  • Publication number: 20220188589
    Abstract: An integrated circuit, a wireless communication card and a wiring structure of an identification mark are provided. The integrated circuit includes a power supply wiring, a ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring that overlap each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.
    Type: Application
    Filed: March 1, 2022
    Publication date: June 16, 2022
    Applicant: Au Optronics Corporation
    Inventors: Shyh-Bin Kuo, Hsiang-Chi Cheng, Sin-Jie Wang, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsing Hung
  • Patent number: 11301740
    Abstract: An integrated circuit, a wireless communication card and a wiring structure of an identification mark are provided. The integrated circuit includes a power supply wiring, a ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring that overlap each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: April 12, 2022
    Assignee: Au Optronics Corporation
    Inventors: Shyh-Bin Kuo, Hsiang-Chi Cheng, Sin-Jie Wang, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsing Hung
  • Publication number: 20210295787
    Abstract: The present disclosure relates to a display device including a backlight circuit, a processing circuit, and a clock generation circuit. The backlight circuit is configured to be driven in response to a control signal. The processing circuit is electrically connected to the backlight circuit and is configured to generate a voltage signal and the control signal. The clock generating circuit is electrically connected to the processing circuit to receive the voltage signal. The processing circuit is configured to adjust the control signal according to a clock frequency of the clock signal.
    Type: Application
    Filed: December 9, 2020
    Publication date: September 23, 2021
    Inventors: Sin-Jie WANG, Kuo-Hsiang CHEN, Hsiang-Chi CHENG, Ya-Ting LIN, Shyh-Bin KUO, Yi-Cheng LAI, Yu-Chih WANG, Chung-Hung CHEN
  • Publication number: 20210183908
    Abstract: A chip is provided. The chip includes a flexible substrate, a plurality of thin-film transistors, a redistribution layer, a first power rail layer, and a second power rail layer. The plurality of thin-film transistors are disposed on the flexible substrate. The redistribution layer is disposed above the plurality of thin-film transistors. The first power rail layer is disposed above the redistribution layer. The first power rail layer provides a first voltage to the plurality of thin-film transistors. The second power rail layer is disposed above the first power rail layer. The second power rail layer provides a second voltage to the plurality of thin-film transistors, wherein the second power rail layer is disposed in a grid shape.
    Type: Application
    Filed: September 26, 2020
    Publication date: June 17, 2021
    Applicant: Au Optronics Corporation
    Inventors: Hsiang-Chi Cheng, Yi-Cheng Lai, Sin-Jie Wang, Shyh-Bin Kuo, Kuo-Hsiang Chen, Yu-Chih Wang, Chung-Hung Chen
  • Publication number: 20210182643
    Abstract: An integrated circuit, a wireless communication card and a wiring structure of an identification mark are provided. The integrated circuit includes a power supply wiring, a ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring that overlap each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.
    Type: Application
    Filed: October 28, 2020
    Publication date: June 17, 2021
    Applicant: Au Optronics Corporation
    Inventors: Shyh-Bin Kuo, Hsiang-Chi Cheng, Sin-Jie Wang, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsing Hung