Patents by Inventor Sin-jin Kim

Sin-jin Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12249718
    Abstract: A negative electrode includes a negative electrode active material layer, wherein the negative electrode active material layer includes a negative electrode active material and a conductive material. The negative electrode active material includes SiOx (0?x<2) particles and the conductive material includes secondary particles in which a portion of one graphene sheet is connected to a portion of an adjacent graphene sheet and a carbon nanotube structure in which 2 to 5,000 single-walled carbon nanotube units are coupled to each other, wherein the oxygen content of the secondary particles is 1 wt % to 10 wt % based on the total weight of the secondary particles, the specific surface area of the secondary particles measured by a nitrogen adsorption BET method is 500 m2/g to 1100 m2/g, and the carbon nanotube structure is included in the negative electrode active material layer in an amount of an 0.01 wt % to 1.0 wt %.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: March 11, 2025
    Assignee: LG Energy Solution, Ltd.
    Inventors: Tae Gon Kim, Ki Won Sung, Wang Mo Jung, Sin Young Park, Dae Jin Lee, Bo Ram Lee, Hak Yoon Kim
  • Patent number: 5293458
    Abstract: Disclosed is a multi-layer neural network and circuit design method.
    Type: Grant
    Filed: August 15, 1991
    Date of Patent: March 8, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-sun Chung, Sin-jin Kim
  • Patent number: 5155699
    Abstract: A divider using neural network configurations comprises a subtractor, a selecting means, a first latch means, a second latch means, a shift register and a control means. The subtractor of the divider comprises plural inverters and plural 3-bit full-adders which are composed of four output lines, an input synapse group, a first bias synapse group, a second bias synapse group, a feedback synapse group, a neuron group and an inverter group.
    Type: Grant
    Filed: July 10, 1990
    Date of Patent: October 13, 1992
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-sun Chung, Sin-jin Kim, Tae-hun Kim
  • Patent number: 5130944
    Abstract: A divider circuit for efficiently and quickly performing a hardware implemented division by adopting a neural network architecture. The circuit includes a series of cascaded subtracter components that complement the divisor input and effectively perform an adder function. The subtracters include a synaptic configuration consisting of PMOS transistors, NMOS transistors, and CMOS inverters. The components are arranged in accordance with the predetermined connection strength assigned to each of the transistors and its respective position in the neural type network arrangement.
    Type: Grant
    Filed: July 9, 1990
    Date of Patent: July 14, 1992
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-sun Chung, Sin-jin Kim, Tae-hun Kim