Abstract: Disclosed is a multi-layer neural network and circuit design method.

Abstract: A divider using neural network configurations comprises a subtractor, a selecting means, a first latch means, a second latch means, a shift register and a control means. The subtractor of the divider comprises plural inverters and plural 3-bit full-adders which are composed of four output lines, an input synapse group, a first bias synapse group, a second bias synapse group, a feedback synapse group, a neuron group and an inverter group.

Abstract: A divider circuit for efficiently and quickly performing a hardware implemented division by adopting a neural network architecture. The circuit includes a series of cascaded subtracter components that complement the divisor input and effectively perform an adder function. The subtracters include a synaptic configuration consisting of PMOS transistors, NMOS transistors, and CMOS inverters. The components are arranged in accordance with the predetermined connection strength assigned to each of the transistors and its respective position in the neural type network arrangement.