Patents by Inventor Sin Leng Lim

Sin Leng Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Planarized passivation layer for semiconductor devices
    Patent number: 8264088
    Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: September 11, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sin Leng Lim, In Ki Kim, Jong Sung Park, Min Hwan Kim, Wei Lu
  • PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES
    Publication number: 20110266688
    Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
    Type: Application
    Filed: July 11, 2011
    Publication date: November 3, 2011
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sin Leng LIM, In Ki KIM, Jong Sung PARK, Min Hwan KIM, Wei LU
  • Planarized passivation layer for semiconductor devices
    Patent number: 7998831
    Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: August 16, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sin Leng Lim, In Ki Kim, Jong Sung Park, Min Hwan Kim, Wei Lu
  • Integrated circuit having ultralow-K dielectric layer
    Patent number: 7829422
    Abstract: A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to subsequently processing, such as curing medium used to form voids in an ultralow-k dielectric layer.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: November 9, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Johnny Widodo, Huang Liu, Sin Leng Lim
  • PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES
    Publication number: 20080246159
    Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 9, 2008
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Sin Leng LIM, In Ki KIM, Jong Sung PARK, Min Hwan KIM, Wei LU
  • Integrated Circuit Having Ultralow-K Dielectric Layer
    Publication number: 20080153310
    Abstract: A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to subsequently processing, such as curing medium used to form voids in an ultralow-k dielectric layer.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Applicant: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Johnny Widodo, Huang Liu, Sin Leng Lim