Abstract: Signal transmission cables and serial interfaces with built-in signal boosting are provided. In some implementations, a signal transmission cable or interface for boosting signals comprises boosting circuitry. The boosting circuitry may comprise at least one boosting capacitor configured to be operatively coupled to a voltage supply during a charging phase and configured to be operatively coupled to the at least one line of a signal transmission cable or interface during a discharging phase, wherein, during the discharging phase, the at least one boosting capacitor boosts a voltage of the one or more signals transmitted on the at least one line. The boosting circuitry may comprise switching circuitry configured to switch the at least one boosting capacitor between from being operatively coupled to the voltage supply to being operatively coupled to the at least one line of the signal transmission cable or interface.

Abstract: Systems and methods for signal boosting in serial interfaces are provided. In some implementations, a system for boosting signals comprises boosting circuitry. The boosting circuitry may comprise at least one boosting capacitor configured to be operatively coupled to a voltage supply during a charging phase and configured to be operatively coupled to the at least one line of a signal transmission line during a discharging phase, wherein, during the discharging phase, the at least one boosting capacitor boosts a voltage of the one or more signals transmitted on the at least one line. The boosting circuitry may comprise switching circuitry configured to switch the at least one boosting capacitor between from being operatively coupled to the voltage supply to being operatively coupled to the at least one line of the signal transmission line.

Abstract: A hub device enables the deployment of I2C devices in a system that also includes I3C devices. The hub has an I3C-compliant interface with which it communicates with an I3C master(s) on an I3C bus, an I2C-compliant interface with which it communicates with I2C devices on an I2C bus, and logic and memory that supports the conversion between the two domains.

Abstract: An apparatus relates generally to an analog switch. In such apparatus, the analog switch has a transistor. A first node of the transistor is coupled to an input node of the analog switch. A second node of the transistor is coupled to an output node of the analog switch. An overvoltage protection circuit is coupled to provide a control voltage to a gate node of the transistor. The overvoltage protection circuit is used to at least substantially reduce an overvoltage state caused by an analog voltage at the input node of the analog switch exceeding an overvoltage threshold voltage.

Abstract: A charge pump for a phase-locked loop (PLL) has accurate matching of charge and discharge currents applied to the PLL's loop filter. A variable current-sink transistor has its gate-to-source voltage adjusted to match a source current from a fixed current source. An intermediate node in-between series transistors between the current source and sink is sampled by a sampling transistor that connects the intermediate node to a sampling capacitor. The sampling capacitor's voltage is the gate-to-source voltage of the variable current-sink transistor. The variable current-sink transistor has its gate and drain coupled together through the sampling transistor during calibration periods when the charge pump is otherwise idle. When the source current exactly matches the sink current, the gate-to-source voltage stored on the sampling capacitor reaches steady state. Up and down currents are balanced in driver transistors that match the series transistors.

Abstract: A charge pump for a phase-locked loop (PLL) has accurate matching of charge and discharge currents applied to the PLL's loop filter. A variable current-sink transistor has its gate-to-source voltage adjusted to match a source current from a fixed current source. An intermediate node in-between series transistors between the current source and sink is sampled by a sampling transistor that connects the intermediate node to a sampling capacitor. The sampling capacitor's voltage is the gate-to-source voltage of the variable current-sink transistor. The variable current-sink transistor has its gate and drain coupled together through the sampling transistor during calibration periods when the charge pump is otherwise idle. When the source current exactly matches the sink current, the gate-to-source voltage stored on the sampling capacitor reaches steady state. Up and down currents are balanced in driver transistors that match the series transistors.

Abstract: A frequency divider circuit is disclosed that generates output signals having a frequency substantially half of the frequency of the input signal. The circuit comprises two D-Flip-Flop circuits wherein one employs the said input signal and the other one employs the complement of the said input signal, and each of the two D-Flip-Flop circuits consists of a pair of loading transistors, two regenerative pairs coupled with each others, and two common-gate switches.

Abstract: A frequency divider circuit is disclosed that generates output signals having a frequency substantially half of the frequency of the input signal. The circuit comprises two D-Flip-Flop circuits wherein one employs the said input signal and the other one employs the complement of the said input signal, and each of the two D-Flip-Flop circuits consists of a pair of loading transistors, two regenerative pairs coupled with each others, and two common-gate switches.

Abstract: A switched capacitor circuit is described that uses two switchable operational amplifiers that operate in parallel and in alternate clock phases. In a preferred embodiment of the invention, the two operational amplifiers may be implemented by a single two-stage operational amplifier having a common input stage and two switchable output pairs. The novel switched capacitor circuit may be used in any application that uses a conventional switched capacitor circuit, such as an integrator and a filter means.