Abstract: Method of forming pn heterojunction between nickel oxide and gallium oxide disclosed. The method includes forming a trench by etching an n-type gallium oxide epitaxial layer epitaxially grown on an n-type gallium oxide substrate using an etch mask, forming a p-type nickel oxide region on the bottom of the trench by sputtering a nickel oxide target on the n-type gallium oxide epitaxial layer in a mixed gas atmosphere of argon and oxygen, and forming a nickel layer on the p-type nickel oxide region by sputtering a nickel target on the n-type gallium oxide epitaxial layer in an argon gas atmosphere.

Abstract: Gallium oxide semiconductor device may include an n-type gallium oxide epitaxial layer epitaxially grown on a gallium oxide substrate, an n-type contact layer formed of indium tin oxide on the n-type gallium oxide epitaxial layer, a metal electrode layer formed on the n-type contact layer, and a diffusion layer extending from a heterojunction between the n-type gallium oxide epitaxial layer and the n-type contact layer toward the n-type gallium oxide epitaxial layer. The diffusion layer may be formed by diffusing the n-type contact layer into the n-type gallium oxide epitaxial layer by a post-annealing.

Abstract: A method for adjusting a channel length of silicon carbide MOSFET includes depositing a buffer layer and a poly-silicon layer on a first conductivity type epitaxial layer having a plurality of second conductivity type bases, etching the poly-silicon layer to form a poly-silicon pattern, depositing a spacer layer on the poly-silicon pattern and exposed buffer layer to a first deposition thickness, forming a first width of spacers of the poly-silicon pattern by dry etching the spacer layer, forming a pair of first conductivity type source regions on the second conductivity type bases by ion implantation into a first pattern mask formed on the buffer layer, forming a second conductivity type source region on the second conductivity type bases by implanting ions into a second pattern mask, and forming a gate electrode on a first channel extending from the first conductivity type source region to the first conductivity type epitaxial layer.

Abstract: Lateral gallium oxide transistor includes a gallium oxide substrate, an n-type gallium oxide epitaxial layer epitaxially grown on the gallium oxide substrate, an insulating layer defining a gate region, a source region, and a drain region on the n-type gallium oxide epitaxial layer, a diffusion barrier layer deposited on the n-type gallium oxide epitaxial layer exposed in the gate region, a p-type nickel oxide layer deposited on the diffusion barrier layer, a dielectric layer deposited on the p-type nickel oxide layer, a gate electrode layer deposited on the dielectric layer, and a source electrode and a drain electrode formed on the n-type gallium oxide epitaxial layer exposed in the source region and the drain region.

Abstract: Schottky diode and method for fabricating the same disclosed. The Schottky diode includes a gallium oxide layer that is a semiconductor layer doped with a first-type dopant, a cathode in ohmic contact with the gallium oxide layer and an anode having a Schottky contact metal layer in Schottky contact with the gallium oxide layer. The gallium oxide layer is in contact with an interface with the Schottky contact metal layer, contains a second-type dopant of a conductivity opposite to that of the first-type dopant, and has an interlayer which is a region where a concentration of the second-type dopant decreases as it moves away from an interface with the Schottky contact metal layer.

Abstract: Tapped inductor boost converter disclosed.

Abstract: Lateral gallium oxide transistor disclosed. Lateral gallium oxide transistor includes a gallium oxide substrate, an n-type gallium oxide epitaxial layer epitaxially grown on the gallium oxide substrate, an insulating layer defining a gate region, a source region, and a drain region on the n-type gallium oxide epitaxial layer, a p-type nickel oxide layer deposited on the n-type gallium oxide epitaxial layer exposed in the gate region, a dielectric layer deposited on the p-type nickel oxide layer, a gate electrode layer deposited on the dielectric layer and a source electrode and a drain electrodes formed on the n-type gallium oxide epitaxial layer exposed in the source region and the drain region.

Abstract: Silicon carbide junction barrier Schottky diode disclosed. Silicon carbide junction barrier Schottky diode includes a first conductivity-type substrate, a first conductivity-type epitaxial layer, being formed by epitaxial growth of silicon carbide doped with a first conductivity-type impurity on the first conductivity-type substrate, a charge injection region, being formed on the first conductivity-type epitaxial layer and doped at a concentration of the first conductivity-type impurity higher than that of the first conductivity-type epitaxial layer, a second conductivity-type junction region, being formed on the first conductivity-type epitaxial layer so as to contact the charge injection region, a Schottky metal layer, being formed on the charge injection region and the second conductivity-type junction region, an anode electrode, being formed on the Schottky metal layer, and a cathode electrode, being formed under the first conductivity-type substrate.

Abstract: Schottky diode and method for fabricating the same disclosed. The Schottky diode includes a gallium oxide layer that is a semiconductor layer doped with a first-type dopant, a cathode in ohmic contact with the gallium oxide layer and an anode having a Schottky contact metal layer in Schottky contact with the gallium oxide layer. The gallium oxide layer is in contact with an interface with the Schottky contact metal layer, contains a second-type dopant of a conductivity opposite to that of the first-type dopant, and has an interlayer which is a region where a concentration of the second-type dopant decreases as it moves away from an interface with the Schottky contact metal layer.

Abstract: Disclosed is a SiC wide trench-type junction barrier Schottky diode. The Schottky diode includes a SiC N? epitaxial layer formed on a SiC N+-type substrate and a Schottky metal layer having a planar Schottky metal pattern layer and a downwardly depressed trench-type Schottky metal pattern layer, which are alternately formed at predetermined intervals and on the upper end part of the SiC N? epitaxial layer. The Schottky diode includes a P+ junction pattern formed so as to permeate from the lower part of the trench-type Schottky metal pattern layer to the SiC N? epitaxial layer and a cathode electrode formed on the lower part of the SiC N+-type substrate. The width of the P+ junction pattern is narrower than the width of the trench-type Schottky metal pattern layer, and the P+ junction pattern is not formed on a side wall vertical surface region of the trench-type Schottky metal pattern layer.

Abstract: Disclosed is a SiC wide trench-type junction barrier Schottky diode. The Schottky diode includes a SiC N? epitaxial layer formed on a SiC N+-type substrate and a Schottky metal layer having a planar Schottky metal pattern layer and a downwardly depressed trench-type Schottky metal pattern layer, which are alternately formed at predetermined intervals and on the upper end part of the SiC N? epitaxial layer. The Schottky diode includes a P+ junction pattern formed so as to permeate from the lower part of the trench-type Schottky metal pattern layer to the SiC N? epitaxial layer and a cathode electrode formed on the lower part of the SiC N+-type substrate. The width of the P+ junction pattern is narrower than the width of the trench-type Schottky metal pattern layer, and the P+ junction pattern is not formed on a side wall vertical surface region of the trench-type Schottky metal pattern layer.

Abstract: Disclosed is a SiC wide trench-type junction barrier Schottky diode. The Schottky diode includes a SiC N? epitaxial layer formed on a SiC N+-type substrate and a Schottky metal layer having a planar Schottky metal pattern layer and a downwardly depressed trench-type Schottky metal pattern layer, which are alternately formed at predetermined intervals and on the upper end part of the SiC N? epitaxial layer. The Schottky diode includes a P+ junction pattern formed so as to permeate from the lower part of the trench-type Schottky metal pattern layer to the SiC N? epitaxial layer and a cathode electrode formed on the lower part of the SiC N+-type substrate. The width of the P+ junction pattern is narrower than the width of the trench-type Schottky metal pattern layer, and the P+ junction pattern is not formed on a side wall vertical surface region of the trench-type Schottky metal pattern layer.

Abstract: Disclosed is a SiC wide trench-type junction barrier Schottky diode. The Schottky diode includes a SiC N? epitaxial layer formed on a SiC N+-type substrate and a Schottky metal layer having a planar Schottky metal pattern layer and a downwardly depressed trench-type Schottky metal pattern layer, which are alternately formed at predetermined intervals and on the upper end part of the SiC N? epitaxial layer. The Schottky diode includes a P+ junction pattern formed so as to permeate from the lower part of the trench-type Schottky metal pattern layer to the SiC N? epitaxial layer and a cathode electrode formed on the lower part of the SiC N+-type substrate. The width of the P+ junction pattern is narrower than the width of the trench-type Schottky metal pattern layer, and the P+ junction pattern is not formed on a side wall vertical surface region of the trench-type Schottky metal pattern layer.