Abstract: In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

Abstract: A bridge includes a memory to establish a transaction table and write combining windows. Each write combining window is associated with a cache line and is subdivided into subwindows; and each of the subwindows is associated with a partial cache line. The bridge includes a controller to determine whether an incoming partial write transaction conflicts with a transaction stored in the transaction table. If a conflict occurs, the controller uses the write combining windows to combine the partial write transaction with another partial write transaction if one of the partial write combining windows is available. The controller issues a retry signal to a processor originating the partial write transaction if none of the partial write combining windows are available.

Abstract: The present invention relates generally to a versatile clip for jewellery which functions as the link between the necklace and exchangeable pieces of jewellery comprising a front member (4) and a rear member (6) having curved profiles and hinged at one end whilst the respective engaging ends (10A), (10B) of the front and rear members (4), (6) opposing the hinge (8) are capable of being integrally latched to assume a central aperture (12); said engaging end (10A) of the front member (4) opposing the hinge (8) is provided with an indented notch (16A) to accommodate a hook (18) having one end (20) permanently fixed on the outer surface (22) of the front member (4) adjacent to the base (16C) of the indented notch (16A) and one unfixed end (24) freely extending into the indented notch (16A); said engaging end (10B) of the rear member (6) opposing the hinge (8) is also provided with an indented notch (16B) to snugly encompass the free unfixed end (24) of the hook (18) to hold the pendant captive when the engaging e

Abstract: Detecting and flushing maximal length packets is set forth herein. In one embodiment, the method comprises receiving a flushing event and, in response to the flushing event, repeatedly detecting a maximum length packet of write data from a write combining storage area and flushing the detected maximum length packet to a target input/output (I/O) device over a bus. Each maximal length packet is a packet of maximum payload of write data that can be formulated within in the write combining storage area while adhering to packet protocol rules for the bus.

Abstract: A forwarding device compares a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict exists. The forwarding device completes a first processor-issued transaction of the at least one processor-issued transaction if the address conflict exists and rejects the first coherent I/O transaction. The forwarding device holds remaining processor transactions of the at least one processor-issued transaction that have an address conflict with the first address of the first coherent I/O transaction. The forwarding device transmits the first coherent I/O transaction to an external I/O device, waits for the first coherent I/O transaction to return from the external I/O device, and completes the first coherent I/O transaction. The forwarding device releases the remaining processor transactions once the first coherent I/O transaction has been completed.

Abstract: A computer system including a slice-addressable multi-port memory array is disclosed. The slice-addressable multi-port memory array provides a mechanism for efficient data merging in a memory controller in accordance with an associated array of slice-enable bits. Each slice of the memory array is individually designated by a slice-enable bit, and only those slices of a word line enabled for writing that are designated by a slice-enable bit are modified during a write operation. In a subsequent write-merge operation, the slices of the word line enabled for writing that were not designated by slice-enable bits during the write operation are modified, and the slices that were modified during the preceding write operation are unaffected, thereby providing for efficient merger of data from the write operation and data from the write-merge operation in a single word line.

Abstract: A computer system including individually resettable bus expander bridges is described. A master bus controller provides an interface between at least one processor and at least one independently resettable bus expander bridge associated with one or more expansion buses. A bus expander bridge can be reset independently from the rest of the system when the master bus controller asserts a reset control signal that is applied to the bus expander bridge without affecting the operation of any other bus expander bridges or devices in the computer system not directly coupled to the expansion bus(es) being reset. When a reset control signal is asserted, the bus expander bridge being reset and the bus(es) associated with the bus expander bridge are reset to a default state. Once the reset process has had sufficient time for completion, the reset control signal is deasserted by the master bus controller and the bus expander bridge resumes operation.