Abstract: Some embodiments relate an integrated circuit (IC) including a first substrate including a plurality of imaging devices. A second substrate is disposed under the first substrate and includes a plurality of logic devices. A first interconnect structure is disposed between the first substrate and the second substrate and electrically couples imaging devices within the first substrate to one another. A second interconnect structure is disposed between the first interconnect structure and the second substrate, and electrically couples logic devices within the second substrate to one another. A bond pad structure is coupled to a metal layer of the second interconnect structure and extends along inner sidewalls of both the first interconnect structure and the second interconnect structure. An oxide layer extends from above the first substrate to below a plurality of metal layers of the first interconnect structure, and lines inner sidewalls of the bond pad structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first integrated chip (IC) tier and a second IC tier. The second IC tier comprises a second plurality of conductors within a second insulating structure disposed on the second semiconductor body. A conductive pad is electrically coupled to the second plurality of conductors and has a conductive surface available to a side of the second semiconductor body facing away from the first semiconductor body. The IC first tier contacts the second IC tier along a bonding interface including one or more conductive regions and one or more insulating regions. The one or more conductive regions laterally outside of a bottom surface of the conductive pad.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip including a substrate having an upper surface vertically below a top surface. A dielectric structure contacts the top surface of the substrate. A conductive structure is disposed in the substrate. The conductive structure includes an upper conductive body and conductive protrusions directly underlying the upper conductive body. The upper conductive body overlies the upper surface of the substrate. A bottom surface of the dielectric structure is disposed between a top surface and a bottom surface of the upper conductive body. An isolation structure is disposed in the substrate on opposing sides of the upper conductive body.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first isolation structure on a first surface of a substrate. A second isolation structure is formed into the first surface of the substrate. Sidewalls of the first isolation structure are disposed laterally between inner sidewalls of the second isolation structure. A bond pad is formed in the substrate such that the second isolation structure continuously laterally wraps around the bond pad.

Abstract: A network system crossing different transmission protocols includes a user device, a first conversion apparatus, a server device and a second conversion apparatus. Data transmission between the first conversion apparatus and the second conversion apparatus is performed in accordance with network addresses of the first conversion apparatus and the second conversion apparatus, and one of transmission control protocol (TCP) and multipath transmission control protocol (MPTCP) is selected for performing the data transmission. A user packet is transmitted between the first conversion apparatus and the user device in accordance with network addresses of the user device and the server device. A server packet is transmitted between the second conversion apparatus and the server device in accordance with the network addresses of the user device and server devices.

Abstract: A photosensing pixel includes a substrate, a photosensing region, a floating diffusion region, a transfer gate and a control electrode. The photosensing region is located within the substrate. The floating diffusion region is located within the substrate aside the photosensing region. The transfer gate is disposed on the substrate and extending into the photosensing region. The control electrode is located on the substrate and extending into the floating diffusion region.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a stilted pad structure. A wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. Further, a trench isolation structure extends into the frontside of the semiconductor substrate. The stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. The stilted pad structure comprises a pad body and a pad protrusion. The pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. The pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate.

Abstract: Some embodiments relate an integrated circuit (IC) including a first substrate including a plurality of imaging devices. A second substrate is disposed under the first substrate and includes a plurality of logic devices. A first interconnect structure is disposed between the first substrate and the second substrate and electrically couples imaging devices within the first substrate to one another. A second interconnect structure is disposed between the first interconnect structure and the second substrate, and electrically couples logic devices within the second substrate to one another. A bond pad structure is coupled to a metal layer of the second interconnect structure and extends along inner sidewalls of both the first interconnect structure and the second interconnect structure. An oxide layer extends from above the first substrate to below a plurality of metal layers of the first interconnect structure, and lines inner sidewalls of the bond pad structure.

Abstract: A photosensing pixel includes a substrate, a photosensing region, a floating diffusion region, a transfer gate and a control electrode. The photosensing region is located within the substrate. The floating diffusion region is located within the substrate aside the photosensing region. The transfer gate is disposed on the substrate and extending into the photosensing region. The control electrode is located on the substrate and extending into the floating diffusion region.

Abstract: A semiconductor device structure is provided, in some embodiments. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface, and sidewalls defining a recess that passes through the semiconductor substrate. The semiconductor device structure further includes an interconnect structure having one or more interconnect layers within a first dielectric structure that is disposed along the second surface. A conductive bonding structure is disposed within the recess and includes nickel. The conductive bonding structure has opposing outermost sidewalls that contact sidewalls of the interconnect structure.

Abstract: Some embodiments relate an integrated circuit (IC). The IC includes a first substrate including an array of photodetectors, wherein a bond pad opening extends through the first substrate and is defined by an inner sidewall of the first substrate. An interconnect structure is disposed over the first substrate and includes a plurality of metal layers stacked over one another and disposed within a dielectric structure. The bond pad opening further extends through at least a portion of the interconnect structure and is further defined by an inner sidewall of the interconnect structure. A bond pad structure directly contacts a metal layer of the plurality of metal layers in the interconnect structure and is located at an uppermost extent of the bond pad opening.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first isolation structure on a first surface of a substrate. A second isolation structure is formed into the first surface of the substrate. Sidewalls of the first isolation structure are disposed laterally between inner sidewalls of the second isolation structure. A bond pad is formed in the substrate such that the second isolation structure continuously laterally wraps around the bond pad.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire disposed within a dielectric structure on a substrate. A bond pad has a lower surface contacting the first interconnect wire. A via layer is vertically between the first interconnect wire and a second interconnect wire within the dielectric structure. The via layer includes a plurality of support vias having a first size and a plurality of additional vias having a second size that is smaller than the first size. The plurality of support vias extend from directly under the lower surface of the bond pad to laterally past outermost edges of the lower surface of the bond pad.

Abstract: A network system crossing different transmission protocols includes a user device, a first conversion apparatus, a server device and a second conversion apparatus. Data transmission between the first conversion apparatus and the second conversion apparatus is performed in accordance with network addresses of the first conversion apparatus and the second conversion apparatus, and one of transmission control protocol (TCP) and multipath transmission control protocol (MPTCP) is selected for performing the data transmission. A user packet is transmitted between the first conversion apparatus and the user device in accordance with network addresses of the user device and the server device. A server packet is transmitted between the second conversion apparatus and the server device in accordance with the network addresses of the user device and server devices.

Abstract: A photosensing pixel includes a substrate, a photosensing region, a floating diffusion region, a transfer gate and a control electrode. The photosensing region is located within the substrate. The floating diffusion region is located within the substrate aside the photosensing region. The transfer gate is disposed on the substrate and extending into the photosensing region. The control electrode is located on the substrate and extending into the floating diffusion region.

Abstract: In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality of interconnect layers within a first dielectric structure on a front-side of a first substrate and forming a second plurality of interconnect layers within a second dielectric structure on a front-side of a second substrate. A first redistribution layer coupled to the first plurality of interconnect layers is bonded to a second redistribution layer coupled to the second plurality of interconnect layers along an interface. A recess is formed within a back-side of the second substrate and over the second plurality of interconnect layers. A bond pad is formed within the recess. The bond pad is laterally separated from the first redistribution layer by a non-zero distance.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device structure including a bond pad isolation structure. A semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. A bond pad extends through the semiconductor substrate. The bond pad isolation structure is disposed within the semiconductor substrate. The bond pad isolation structure extends from the front-side surface to the back-side surface of the semiconductor substrate and continuously extends around the bond pad.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device structure including a bond pad isolation structure. A semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. A bond pad extends through the semiconductor substrate. The bond pad isolation structure is disposed within the semiconductor substrate. The bond pad isolation structure extends from the front-side surface to the back-side surface of the semiconductor substrate and continuously extends around the bond pad.