Patents by Inventor Sin-Yi Yang

Sin-Yi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY DEVICE AND FABRICATION METHOD THEREOF
    Publication number: 20200106007
    Abstract: A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.
    Type: Application
    Filed: November 16, 2018
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
  • Metal Etching Stop Layer in Magnetic Tunnel Junction Memory Cells
    Publication number: 20200106008
    Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
    Type: Application
    Filed: April 1, 2019
    Publication date: April 2, 2020
    Inventors: Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Chih-Yuan Ting
  • INTEGRATED CIRCUIT AND FABRICATION METHOD THEREOF
    Publication number: 20200066580
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 27, 2020
    Inventors: Tai-Yen PENG, Chang-Sheng LIN, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20200035907
    Abstract: The present disclosure provides a semiconductor structure, including a bottom electrode via, a top surface of the bottom electrode via having a first width, a barrier layer surrounding the bottom electrode via, and a magnetic tunneling junction (MTJ) over the bottom electrode via, a bottom of the MTJ having a second width, the first width being narrower than the second width.
    Type: Application
    Filed: January 8, 2019
    Publication date: January 30, 2020
    Inventors: TAI-YEN PENG, YU-SHU CHEN, CHIEN CHUNG HUANG, SIN-YI YANG, CHEN-JUNG WANG, HAN-TING LIN, JYU-HORNG SHIEH, QIANG FU
  • Semiconductor Device and Methods of Manufacture
    Publication number: 20190148553
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 16, 2019
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Semiconductor device and methods of manufacture
    Patent number: 10164111
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Semiconductor Device and Methods of Manufacture
    Publication number: 20180040733
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Application
    Filed: December 29, 2016
    Publication date: February 8, 2018
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng