Patents by Inventor Sing-Kai Huang
Sing-Kai Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11152348Abstract: An integrated circuit structure includes: a first plurality of cell rows extending in a first direction, each of which has a first row height and comprises a plurality of first cells disposed therein; and a second plurality of cell rows extending in the first direction, each of which has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction, and wherein the plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction.Type: GrantFiled: November 20, 2018Date of Patent: October 19, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kam-Tou Sio, Jiann-Tyng Tzeng, Jack Liu, Yi-Chuin Tsai, Shang-Wei Fang, Sing-Kai Huang, Charles Chew-Yuen Young
-
Patent number: 11145678Abstract: A method for manufacturing a semiconductor device includes following operations. A substrate including an active area is received. A plurality of source/drain regions of a plurality of transistor devices are formed in the active area. An isolation region is inserted between two adjacent source/drain regions of two adjacent transistor devices. The isolation region and the two adjacent source/drain regions cooperatively form two diode devices electrically connected in a back to back manner.Type: GrantFiled: December 4, 2019Date of Patent: October 12, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jack Liu, Jiann-Tyng Tzeng, Chih-Liang Chen, Chew-Yuen Young, Sing-Kai Huang, Ching-Fang Huang
-
Patent number: 11127626Abstract: A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface is leveled with the first surface; and forming an alignment structure on the top surface. The method further includes forming a photoresist on the alignment layer to cover a portion of the top surface; and removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface. The method further includes forming a dielectric surrounding the alignment structure on the first surface and over the alignment structure, removing a portion of the dielectric to expose the alignment structure by CMP; removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.Type: GrantFiled: September 26, 2020Date of Patent: September 21, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jack Liu, Wei-Cheng Wu, Charles Chew-Yuen Young, Sing-Kai Huang
-
Patent number: 11062745Abstract: Some embodiments relate to a sense amplifier. The sense amplifier includes a fully-depleted silicon on insulator (FDSOI) substrate, including a handle substrate region, an insulator layer over the handle substrate region, and a device region over the insulator layer. An n-well region is disposed in the handle substrate region, and an n-well contact region extends from the n-well region through the insulator layer to an upper surface of the device region. A pair of pull-down transistors are disposed in the device region and over the n-well. The pair of pull-down transistors have their respective gates coupled to a pair of complementary bitlines, respectively, and coupled to the n-well through the n-well contact region.Type: GrantFiled: May 13, 2019Date of Patent: July 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sing-Kai Huang, Charles Chew-Yuen Young, Jack Liu
-
Publication number: 20210013094Abstract: A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface is leveled with the first surface; and forming an alignment structure on the top surface. The method further includes forming a photoresist on the alignment layer to cover a portion of the top surface; and removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface. The method further includes forming a dielectric surrounding the alignment structure on the first surface and over the alignment structure, removing a portion of the dielectric to expose the alignment structure by CMP; removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.Type: ApplicationFiled: September 26, 2020Publication date: January 14, 2021Inventors: JACK LIU, WEI-CHENG WU, CHARLES CHEW-YUEN YOUNG, SING-KAI HUANG
-
Patent number: 10796947Abstract: A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is substantially level with the first surface; and forming an alignment structure on the top surface of the gate electrode. The method further includes forming a dielectric surrounding the alignment structure on the first surface, removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.Type: GrantFiled: December 12, 2018Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jack Liu, Wei-Cheng Wu, Charles Chew-Yuen Young, Sing-Kai Huang
-
Publication number: 20200194303Abstract: A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is substantially level with the first surface; and forming an alignment structure on the top surface of the gate electrode. The method further includes forming a dielectric surrounding the alignment structure on the first surface, removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: JACK LIU, WEI-CHENG WU, CHARLES CHEW-YUEN YOUNG, SING-KAI HUANG
-
Publication number: 20200105313Abstract: Some embodiments relate to a sense amplifier. The sense amplifier includes a fully-depleted silicon on insulator (FDSOI) substrate, including a handle substrate region, an insulator layer over the handle substrate region, and a device region over the insulator layer. An n-well region is disposed in the handle substrate region, and an n-well contact region extends from the n-well region through the insulator layer to an upper surface of the device region. A pair of pull-down transistors are disposed in the device region and over the n-well. The pair of pull-down transistors have their respective gates coupled to a pair of complementary bitlines, respectively, and coupled to the n-well through the n-well contact region.Type: ApplicationFiled: May 13, 2019Publication date: April 2, 2020Inventors: Sing-Kai Huang, Charles Chew-Yuen Young, Jack Liu
-
Publication number: 20200105795Abstract: A method for manufacturing a semiconductor device includes following operations. A substrate including an active area is received. A plurality of source/drain regions of a plurality of transistor devices are formed in the active area. An isolation region is inserted between two adjacent source/drain regions of two adjacent transistor devices. The isolation region and the two adjacent source/drain regions cooperatively form two diode devices electrically connected in a back to back manner.Type: ApplicationFiled: December 4, 2019Publication date: April 2, 2020Inventors: JACK LIU, JIANN-TYNG TZENG, CHIH-LIANG CHEN, CHEW-YUEN YOUNG, SING-KAI HUANG, CHING-FANG HUANG
-
Patent number: 10510776Abstract: A semiconductor device includes a substrate, a pair of transistor devices and an isolation region. The pair of transistor devices are disposed over the substrate. Each of the pair of the transistor devices includes a channel, a gate electrode over the channel, and a source/drain region alongside the gate electrode. The isolation region is disposed between the source/drain regions of the pair of the transistor devices. The isolation region has a first doping type opposite to a second doping type of the source/drain regions.Type: GrantFiled: March 29, 2018Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jack Liu, Jiann-Tyng Tzeng, Chih-Liang Chen, Chew-Yuen Young, Sing-Kai Huang, Ching-Fang Huang
-
Publication number: 20190305006Abstract: A semiconductor device includes a substrate, a pair of transistor devices and an isolation region. The pair of transistor devices are disposed over the substrate. Each of the pair of the transistor devices includes a channel, a gate electrode over the channel, and a source/drain region alongside the gate electrode. The isolation region is disposed between the source/drain regions of the pair of the transistor devices. The isolation region has a first doping type opposite to a second doping type of the source/drain regions.Type: ApplicationFiled: March 29, 2018Publication date: October 3, 2019Inventors: JACK LIU, JIANN-TYNG TZENG, CHIH-LIANG CHEN, CHEW-YUEN YOUNG, SING-KAI HUANG, CHING-FANG HUANG
-
Publication number: 20190164949Abstract: An integrated circuit structure includes: a first plurality of cell rows extending in a first direction, each of which has a first row height and comprises a plurality of first cells disposed therein; and a second plurality of cell rows extending in the first direction, each of which has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction, and wherein the plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction.Type: ApplicationFiled: November 20, 2018Publication date: May 30, 2019Inventors: Kam-Tou SIO, Jiann-Tyng Tzeng, Jack Liu, Yi-Chuin Tsai, Shang-Wei Fang, Sing-Kai Huang