Patents by Inventor Sing-Mo Tzeng

Sing-Mo Tzeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fabricating low K dielectric interconnect systems by using dummy structures to enhance process
    Patent number: 6309956
    Abstract: The present invention relates to semiconductor devices. More specifically, the invention discloses the use of dummy structures to improve thermal conductivity, reduce dishing and strengthen layers formed with low dielectric constant materials.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: October 30, 2001
    Assignee: Intel Corporation
    Inventors: Chien Chiang, David B. Fraser, Anne S. Mack, Jin Lee, Sing-Mo Tzeng, Chuanbin Pan, Vicky Ochoa, Thomas Marieb, Sychyi Fang
  • Interconnect structure and method to achieve unlanded vias for low dielectric constant materials
    Patent number: 5935868
    Abstract: A method of forming an interconnect structure using a low dielectric constant material as an intralayer dielectric is described. In one embodiment, the present inventive method comprises the following steps. A conductive structure that is surrounded by a low dielectric constant material on its side surfaces is formed. A first inorganic insulator is formed over at least a portion of the low dielectric constant material. A second inorganic insulator is formed over the first inorganic insulator. A photoresist layer is deposited and then patterned to form an unlanded via in the second inorganic insulator. The second inorganic insulator and a portion of the first inorganic insulator are etched in order to form the unlanded via.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: August 10, 1999
    Assignee: Intel Corporation
    Inventors: Sychyi Fang, Chaunbin Pan, Sing-Mo Tzeng, Chien Chiang
  • Method of using additives with silica-based slurries to enhance selectivity in metal CMP
    Patent number: 5614444
    Abstract: A method of using additives with silica-based slurries to enhance metal selectivity in polishing metallic materials utilizing a chemical-mechanical polishing (CMP) process. Additives are used with silica-based slurries to passivate a dielectric surface, such as a silicon dioxide (SiO.sub.2) surface, of a semiconductor wafer so that dielectric removal rate is reduced when CMP is applied. The additive is comprised of at least a polar component and an apolar component. The additive interacts with the surface silanol group of the SiO.sub.2 surface to inhibit particles of the silica-based slurry from interacting with hydroxyl molecules of the surface silanol group. By applying a surface passivation layer on the SiO.sub.2 surface, erosion of the SiO.sub.2 surface is reduced. However, the metallic surface is not influenced significantly by the additive, so that the selectivity of metal removal over oxide removal is enhanced.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: March 25, 1997
    Assignees: Sematech, Inc., Intel Corporation, National Semiconductor Corp., Digital Equipment Corp.
    Inventors: Janos Farkas, Rahul Jairath, Matt Stell, Sing-Mo Tzeng