Abstract: A CMOS circuit is disclosed for translating a signal from CML to CMOS logic voltage levels. The CMOS circuit includes two amplifier circuits coupled in parallel. The first amplifier circuit comprises of a programmable circuit and a CMOS inverter such that the CMOS inverter can be programmed "on" or "off" by the programmable circuit. The programmable circuit includes a programmable element which may be implemented using a fuse or floating gate technology. The second amplifying circuit comprises of a CMOS inverter. When the CMOS inverter in the first amplifier circuit is powered "on", the CMOS circuit is operating in a full power mode at high speed with both CMOS inverters operating. When the CMOS inverter in the first amplifier circuit is powered "off", the CMOS circuit is operating in a low power mode at a slower speed with only one CMOS inverter operating.

Abstract: An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, and clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.

Abstract: A programmable array logic cell 60 including a sum-of-products array having a single OR gate 70 for providing a sum signal, and including an XOR gate 80 for combining the sum signal with a product signal provided by an AND gate 78 from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.

Abstract: A TTL inverting output circuit (50) which uses the collector (65) of a parallel phase splitter transistor (Q11) where the voltage changes in phase with the circuit output signal Io to control an active circuit (70) which diverts charge from the base (23) of the output pull-down transistor (Q3).

Abstract: A programmable read-only memory (40) is provided which is capable of storing a plurality of initialize words. The memory includes an initialize input lead (9) and appropriate addressing circuitry (7) so that when the appropriate initialize input signal is placed on the initialize input lead, one of several pre-programmed initialize words is placed in the output register (6) of the programmable read-only memory. The word that is placed in the output register is selected according to signals applied to selected address input leads (A.sub.0 through A.sub.3) of the programmable read-only memory. The number of address input signals utilized to determine which initialize word is placed in the output register of the programmable read-only memory is a selected subset of the available address input signals provided to the memory. The described embodiment provides sixteen initialize words using a minimum number of components.

Abstract: A current source for powering programmable arrays which provides means of eliminating the current supplied to portions of the array which are unimportant to the boolean arithmetic equation which the programmable array is programmed to model. The circuit includes fusible links (33-1 through 33-M) between the current source and portions of the circuit which may be unnecessary. Also included is means of opening (13-1 through 13-M) the fusible links (33-1 through 33-M) which connect the current source with the elements of the programmable array which may be unnecessary, thereby saving the power used to generate the current which would have been wasted in driving the unnecessary portions of the programmable array.

Abstract: A programmable array logic circuit is provided having a programmable AND gate array and having means for connecting individual AND gate outputs to the input of one or the other of a pair of neighboring OR gates. This allows the product terms to be shared between two outputs.