Abstract: To mitigate collisions in a physical space during gaming, a set of physical objects and a user situated in the 3D space are mapped to determine a spacing between an object in the set of physical objects and the user, where the user moves in the 3D space to cause a motion in a virtual environment of a game. A prediction is computed that the user will make a motion in the 3D space during the gaming. For the motion in the 3D space, a motion trajectory of the user is computed using a measurement parameter corresponding to the user stored in a user profile. A detection is made that the motion trajectory of the user violates a spacing threshold between the user and the object, and the user is alerted about a risk of collision between the user and the object in the 3D space.

Abstract: To mitigate collisions in a physical space during gaming, a set of physical objects and a user situated in the 3D space are mapped to determine a spacing between an object in the set of physical objects and the user, where the user moves in the 3D space to cause a motion in a virtual environment of a game. A prediction is computed that the user will make a motion in the 3D space during the gaming. For the motion in the 3D space, a motion trajectory of the user is computed using a measurement parameter corresponding to the user stored in a user profile. A detection is made that the motion trajectory of the user violates a spacing threshold between the user and the object, and the user is alerted about a risk of collision between the user and the object in the 3D space.

Abstract: An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance wit