Abstract: After forming first catalyst cores on the surfaces of adhesive layers of an insulating substrate, a plating resist is patterned. The insulating substrate is treated with an aqueous solution containing an anionic surfactant. Then, the insulating substrate is soaked successively in a palladium—tin mixed colloid catalyst solution and an accelerator solution, whereby second catalyst cores are formed on the surface of the adhesive layer not covered with the plating resist. Thereafter, conductive circuits are formed by electroless copper plating. Due to the anionic surfactant, adsorption of the palladium—tin mixed colloid catalyst to the plating resist is suppressed, and the first catalyst cores promote the formation of second catalyst cores. By setting the concentration of the first catalyst cores to 4×10−8 atomic mol/cm2 or less, a fine conductive circuit with a line width/line space of 50 &mgr;m or less having a high electrical insulating property between circuit lines can be formed.

Abstract: In a multilayer printed circuit board having a conductor pattern, covered with an insulation layer having via holes, these via holes are filled with a conductor by means of electroless nickel plating or electroless copper plating.

Abstract: After forming first catalyst cores on the surfaces of adhesive layers of an insulating substrate, a plating resist is patterned. The insulating substrate is treated with an aqueous solution containing an anionic surfactant. Then, the insulating substrate is soaked successively in a palladium—tin mixed colloid catalyst solution and an accelerator solution, whereby second catalyst cores are formed on the surface of the adhesive layer not covered with the plating resist. Thereafter, conductive circuits are formed by electroless copper plating. Due to the anionic surfactant, adsorption of the palladium—tin mixed colloid catalyst to the plating resist is suppressed, and the first catalyst cores promote the formation of second catalyst cores. By setting the concentration of the first catalyst cores to 4×10−8 atomic mol/cm2 or less, a fine conductive circuit with a line width/line space of 50 &mgr;m or less having a high electrical insulating property between circuit lines can be formed.

Abstract: In a multilayer printed circuit board having a conductor pattern, covered with an insulation layer having via holes, these via holes are filled with a conductor by means of electroless nickel plating or electroless copper plating.