Abstract: A delay buffer unit and an operating method thereof, a computing device and an operating method thereof. The delay buffer unit includes a first-stage inverter, a second-stage inverter and a delay adjustment sub-unit, an input terminal of the first-stage inverter serves as an input terminal of the delay buffer unit; an input terminal of the second-stage inverter is connected with an output terminal of the first-stage inverter, and an output terminal of the second-stage inverter serves as an output terminal of the delay buffer unit; the delay adjustment sub-unit is connected between a first terminal of the first-stage inverter and a first operating voltage terminal, and the delay adjustment sub-unit includes a memristor and is configured to adjust a transmission delay of the first-stage inverter by controlling and using the memristor according to a first control signal.

Abstract: An analog-to-digital conversion circuit, an electronic apparatus, and an operation method are provided. The analog-to-digital conversion circuit includes: An analog-to-digital conversion circuit, including: a clamping module, coupled to a load circuit through a clamping point, where the load circuit provides a load current during working; a bias current generation module, coupled to the clamping module through the clamping point and configured to provide a bias current to the clamping point; and a quantization module, coupled to the clamping module through the clamping point and a first node, configured to provide a bias voltage to the clamping module through the first node to obtain a clamping branch current that is input into the clamping point, and further configured to provide a first current to the clamping point and regulate the first current based on a comparison result of the bias current and the clamping branch current to quantize the load current.

Abstract: A delay buffer unit and an operating method thereof, a computing device and an operating method thereof. The delay buffer unit includes a first-stage inverter, a second-stage inverter and a delay adjustment sub-unit, an input terminal of the first-stage inverter serves as an input terminal of the delay buffer unit; an input terminal of the second-stage inverter is connected with an output terminal of the first-stage inverter, and an output terminal of the second-stage inverter serves as an output terminal of the delay buffer unit; the delay adjustment sub-unit is connected between a first terminal of the first-stage inverter and a first operating voltage terminal, and the delay adjustment sub-unit includes a memristor and is configured to adjust a transmission delay of the first-stage inverter by controlling and using the memristor according to a first control signal.