Abstract: An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.

Abstract: An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.

Abstract: A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

Abstract: A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

Abstract: A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

Abstract: A delay cell for use in a voltage controlled oscillator includes a differential amplifier having a pair of outputs, a common source resistive element supplying current to said differential amplifier, a varactor arrangement between the outputs having a control input, and a pair of load resistive elements connected to the respective outputs. The delay cell has a simple design, a small die area, low power dissipation, constant amplitude of oscillation versus control voltage, and a Figure of Merit (FOM) comparable to that of LC oscillators.

Abstract: A delay cell for use in a voltage controlled oscillator includes a differential amplifier having a pair of outputs, a common source resistive element supplying current to said differential amplifier, a varactor arrangement between the outputs having a control input, and a pair of load resistive elements connected to the respective outputs. The delay cell has a simple design, a small die area, low power dissipation, constant amplitude of oscillation versus control voltage, and a Figure of Merit (FOM) comparable to that of LC oscillators.