Patents by Inventor SinJae Lee
SinJae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12574862Abstract: A communication device and an image display apparatus including the same are disclosed. A communication device of an embodiment of the present disclosure includes a first antenna and a second antenna to receive or transmit a wireless signal of a first and a second communication standard, respectively, and a processor to receive and process a signal or to transmit a processed signal, wherein, in case in which the second antenna receives a wireless signal while the first antenna wirelessly receives first data and wirelessly transmits information related to the first data with a first power, the processor is configured to wirelessly transmit the information related to the first data with a second power lower than the first power. Accordingly, wireless reception performance can be stably secured during wireless communication based on a plurality of communication standards.Type: GrantFiled: May 31, 2023Date of Patent: March 10, 2026Assignee: LG ELECTRONICS INC.Inventor: Sinjae Lee
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Patent number: 12511803Abstract: An electronic device comprises: a display, a processor operatively connected to the display, and a memory operatively connected to the processor. The memory may include instructions that, when executed, cause the processor to: detect events related to the display of content; apply a gradient graphic effect to at least a partial region of a background image based on a distance from a first region in which the content is displayed; and display, through the display, the background image and the content that has had the gradient graphic effect applied thereto.Type: GrantFiled: December 22, 2022Date of Patent: December 30, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woohyun Kim, Sinjae Lee, Sangheon Kim, Wujong Kwon, Chansu Ahn, Yeunwook Lim
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Publication number: 20230397124Abstract: A communication device and an image display apparatus including the same are disclosed. A communication device of an embodiment of the present disclosure includes a first antenna and a second antenna to receive or transmit a wireless signal of a first and a second communication standard, respectively, and a processor to receive and process a signal or to transmit a processed signal, wherein, in case in which the second antenna receives a wireless signal while the first antenna wirelessly receives first data and wirelessly transmits information related to the first data with a first power, the processor is configured to wirelessly transmit the information related to the first data with a second power lower than the first power. Accordingly, wireless reception performance can be stably secured during wireless communication based on a plurality of communication standards.Type: ApplicationFiled: May 31, 2023Publication date: December 7, 2023Applicant: LG ELECTRONICS INC.Inventor: Sinjae Lee
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Publication number: 20230129264Abstract: An electronic device comprises: a display, a processor operatively connected to the display, and a memory operatively connected to the processor. The memory may include instructions that, when executed, cause the processor to: detect events related to the display of content; apply a gradient graphic effect to at least a partial region of a background image based on a distance from a first region in which the content is displayed; and display, through the display, the background image and the content that has had the gradient graphic effect applied thereto.Type: ApplicationFiled: December 22, 2022Publication date: April 27, 2023Inventors: Woohyun KIM, Sinjae LEE, Sangheon KIM, Wujong KWON, Chansu AHN, Yeunwook LIM
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Patent number: 9401347Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.Type: GrantFiled: January 20, 2015Date of Patent: July 26, 2016Assignee: STATS ChipPAC Pte. Ltd.Inventors: SinJae Lee, JinGwan Kim, JiHoon Oh, JaeHyun Lim, KyuWon Lee
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Patent number: 9379064Abstract: A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer.Type: GrantFiled: April 28, 2015Date of Patent: June 28, 2016Assignee: STATS ChipPAC Pte. Ltd.Inventors: JiHoon Oh, SinJae Lee, JinGwan Kim
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Publication number: 20150228590Abstract: A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer.Type: ApplicationFiled: April 28, 2015Publication date: August 13, 2015Applicant: STATS ChipPAC, Ltd.Inventors: JiHoon Oh, SinJae Lee, JinGwan Kim
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Patent number: 9048209Abstract: A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer.Type: GrantFiled: July 25, 2011Date of Patent: June 2, 2015Assignee: STATS ChipPAC, Ltd.Inventors: JiHoon Oh, SinJae Lee, JinGwan Kim
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Publication number: 20150137334Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.Type: ApplicationFiled: January 20, 2015Publication date: May 21, 2015Applicant: STATS ChipPAC, Ltd.Inventors: SinJae Lee, JinGwan Kim, JiHoon Oh, JaeHyun Lim, KyuWon Lee
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Patent number: 8937371Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.Type: GrantFiled: July 3, 2013Date of Patent: January 20, 2015Assignee: STATS ChipPAC, Ltd.Inventors: SinJae Lee, JinGwan Kim, JiHoon Oh, JaeHyun Lim, KyuWon Lee
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Patent number: 8836114Abstract: A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure.Type: GrantFiled: November 16, 2012Date of Patent: September 16, 2014Assignee: STATS ChipPAC, Ltd.Inventors: JiHoon Oh, SinJae Lee, JinGwan Kim
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Publication number: 20130292804Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.Type: ApplicationFiled: July 3, 2013Publication date: November 7, 2013Inventors: SinJae Lee, JinGwan Kim, JiHoon Oh, JaeHyun Lim, KyuWon Lee
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Patent number: 8569870Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a bottom integrated circuit over the substrate; connecting a bottom interconnect between the bottom integrated circuit and the substrate; and mounting a bottom shield-spacer above the bottom integrated circuit and the bottom shield-spacer includes a bottom shield plate above the bottom integrated circuit, a bottom shield pillar extending from a bottom shield foot and connected to the bottom shield plate, and a protuberance extending vertically above the bottom shield pillar and directly above the bottom shield foot.Type: GrantFiled: June 25, 2012Date of Patent: October 29, 2013Assignee: Stats Chippac Ltd.Inventors: SinJae Lee, JongVin Park, Sung Jun Yoon, JiHoon Oh
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Patent number: 8531012Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.Type: GrantFiled: October 23, 2009Date of Patent: September 10, 2013Assignee: STATS ChipPAC, Ltd.Inventors: SinJae Lee, JinGwan Kim, JiHoon Oh, JaeHyun Lim, KyuWon Lee
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Patent number: 8343810Abstract: A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure.Type: GrantFiled: August 16, 2010Date of Patent: January 1, 2013Assignee: STATS ChipPAC, Ltd.Inventors: JiHoon Oh, SinJae Lee, JinGwan Kim
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Publication number: 20120038053Abstract: A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure.Type: ApplicationFiled: August 16, 2010Publication date: February 16, 2012Applicant: STATS CHIPPAC, LTD.Inventors: JiHoon Oh, SinJae Lee, JinGwan Kim
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Publication number: 20110278705Abstract: A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer.Type: ApplicationFiled: July 25, 2011Publication date: November 17, 2011Applicant: STATS CHIPPAC, LTD.Inventors: JiHoon Oh, SinJae Lee, JinGwan Kim
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Patent number: 8003496Abstract: A semiconductor device is made by forming a heat spreader over a temporary carrier. A semiconductor die is mounted to the heat spreader. A first polymer layer is formed over the semiconductor die and heat spreader. A first conductive layer is formed over the first polymer layer. The first conductive layer is connected to the heat spreader and contact pads on the semiconductor die. A second polymer layer is formed over the first conductive layer. A second conductive layer is formed over the second polymer layer. The second conductive layer is electrically connected to the first conductive layer. Bumps are formed through a solder masking layer on the second conductive layer. The temporary carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first and second conductive layers.Type: GrantFiled: August 14, 2009Date of Patent: August 23, 2011Assignee: STATS ChipPAC, Ltd.Inventors: JiHoon Oh, SinJae Lee, JinGwan Kim
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Patent number: 8004093Abstract: An integrated circuit package stacking system includes: forming a flexible substrate by: providing an insulating material, forming a stacking pad on the insulating material, forming a coupling pad on the insulating material, and forming a trace between the stacking pad and the coupling pad; providing a package substrate; coupling an integrated circuit to the package substrate; and applying a conductive adhesive on the package substrate for positioning the flexible substrate over the integrated circuit and coupling the flexible substrate on the conductive adhesive.Type: GrantFiled: August 1, 2008Date of Patent: August 23, 2011Assignee: Stats Chippac Ltd.Inventors: JiHoon Oh, JinGwan Kim, Jaehyun Lim, SunYoung Chun, KyuWon Lee, SinJae Lee, JongVin Park
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Publication number: 20110095403Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.Type: ApplicationFiled: October 23, 2009Publication date: April 28, 2011Applicant: STATS CHIPPAC, LTD.Inventors: SinJae Lee, JinGwan Kim, JiHoon Oh, JaeHyun Lim, KyuWon Lee