Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

Abstract: An object of the present invention is to provided a semiconductor device that permits easy and efficient testing. A semiconductor device which is characterized in that the power supply for an output circuit is selectable between a normal power supply and an independent power supply provided independently of the normal supply.

Abstract: A semiconductor memory has a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a differential sense amplifier, and load transistors. Each of the memory cells is a MIS transistor formed at each intersection of the word and bit lines. The threshold voltage of the MIS transistor is externally electrically controllable. The differential sense amplifier senses data stored in a selected memory cell located at an intersection of selected word and bit lines. A control pulse signal is applied to the gates of the load transistors, to bias the bit lines. The pulse width of the control pulse signal is a minimum essential to read data out of the selected memory cell. The control pulse signal controls the switching of the load transistors, to shorten a period during which a stress voltage is continuously applied to the drains of unselected memory cells that are connected to the bit line to which the selected memory cell is connected.

Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

Abstract: A semiconductor device is disclosed which is directed to drastically reduce a conduction test time by reliably executing the conduction test of all terminals in a lump. The invention discloses the semiconductor device including a first power supply terminal, a second power supply terminal having a lower potential than the first power supply terminal, an internal circuit portion to which the first and second power supply terminals are connected, and an input signal terminal group and an output signal terminal group each connected to the internal circuit portion, wherein a first voltage supply source and a second voltage supply source having a predetermined potential difference from the first voltage supply source are disposed, a switching device is interposed between the first and second voltage supply sources, and the switching device is turned ON and OFF in accordance with the existence of a voltage applied to each of the terminals described above.

Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory including word lines WLi and bit lines BLi, a memory cell matrix 17 including nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

Abstract: A control gate formed on top of an insulation layer over a floating gate for a transistor element of a memory cell in a redundancy ROM is shaped in a form covering not only the top but also the sides of the floating gate. A drain electrode wiring conventionally connected through a well is directly connected to a drain diffusion area. This enables the redundancy ROM to be miniaturized and the voltage fall at the edge of a drain diffusion area to be reduced.