Patents by Inventor Sion Quinlan

Sion Quinlan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190219763
    Abstract: Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a plurality of photonic sources, a plurality of memory die, a logic die. Each of the plurality of photonic sources provides a photonic signal of a different wavelength and are provided to a first photonic path. Each memory die of the plurality of memory die includes a photonic modulation circuit coupled to the first photonic path, and further includes a photonic detector circuit coupled to a second photonic path. Each memory die of the plurality of memory die is associated with and addressed by a respective wavelength of a photonic signal. The logic die is coupled to the first and second photonic paths, and includes a plurality of photonic circuits. Each of the photonic circuits of the plurality of photonic circuits is associated with a respective wavelength of a photonic signal.
    Type: Application
    Filed: March 27, 2019
    Publication date: July 18, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sion Quinlan
  • Patent number: 10274675
    Abstract: Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a plurality of photonic sources, a plurality of memory die, a logic die. Each of the plurality of photonic sources provides a photonic signal of a different wavelength and are provided to a first photonic path. Each memory die of the plurality of memory die includes a photonic modulation circuit coupled to the first photonic path, and further includes a photonic detector circuit coupled to a second photonic path. Each memory die of the plurality of memory die is associated with and addressed by a respective wavelength of a photonic signal. The logic die is coupled to the first and second photonic paths, and includes a plurality of photonic circuits. Each of the photonic circuits of the plurality of photonic circuits is associated with a respective wavelength of a photonic signal.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Sion Quinlan
  • Publication number: 20180120505
    Abstract: Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a plurality of photonic sources, a plurality of memory die, a logic die. Each of the plurality of photonic sources provides a photonic signal of a different wavelength and are provided to a first photonic path. Each memory die of the plurality of memory die includes a photonic modulation circuit coupled to the first photonic path, and further includes a photonic detector circuit coupled to a second photonic path. Each memory die of the plurality of memory die is associated with and addressed by a respective wavelength of a photonic signal. The logic die is coupled to the first and second photonic paths, and includes a plurality of photonic circuits. Each of the photonic circuits of the plurality of photonic circuits is associated with a respective wavelength of a photonic signal.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 3, 2018
    Applicant: Micron Technology, Inc.
    Inventor: SION QUINLAN
  • Patent number: 9885827
    Abstract: Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a plurality of photonic sources, a plurality of memory die, a logic die, Each of the plurality of photonic sources provides a photonic signal of a different wavelength and are provided to a first photonic path. Each memory die of the plurality of memory die includes a photonic modulation circuit coupled to the first photonic path, and further includes a photonic detector circuit coupled to a second photonic path. Each memory die of the plurality of memory die is associated with and addressed by a respective wavelength of a photonic signal. The logic die is coupled to the first and second photonic paths, and includes a plurality of photonic circuits. Each of the photonic circuits of the plurality of photonic circuits is associated with a respective wavelength of a photonic signal.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Sion Quinlan
  • Publication number: 20170269299
    Abstract: Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a plurality of photonic sources, a plurality of memory die, a logic die, Each of the plurality of photonic sources provides a photonic signal of a different wavelength and are provided to a first photonic path. Each memory die of the plurality of memory die includes a photonic modulation circuit coupled to the first photonic path, and further includes a photonic detector circuit coupled to a second photonic path. Each memory die of the plurality of memory die is associated with and addressed by a respective wavelength of a photonic signal. The logic die is coupled to the first and second photonic paths, and includes a plurality of photonic circuits. Each of the photonic circuits of the plurality of photonic circuits is associated with a respective wavelength of a photonic signal.
    Type: Application
    Filed: June 8, 2017
    Publication date: September 21, 2017
    Applicant: Micron Technology, Inc.
    Inventor: Sion Quinlan
  • Publication number: 20170242190
    Abstract: Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a photonic source layer that provides a plurality of photonic sources, each at a different wavelength, a plurality of second layers, and a third layer. Each of the plurality of second layers may be associated with a respective wavelength, and each of the plurality of second layers may include photonic filters tuned to their respective wavelength, a photonic modulator, and a photonic detector. The third layer may include a plurality of photonic circuits, with each of the plurality of photonic circuits associated with a respective second layer of the plurality of second layers. Additionally, each of the plurality of photonic circuits may include a photonic filter tuned to a respective wavelength associated with a respective second layer, a photonic detector and a photonic modulator.
    Type: Application
    Filed: February 18, 2016
    Publication date: August 24, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sion Quinlan
  • Patent number: 9739939
    Abstract: Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a photonic source layer that provides a plurality of photonic sources, each at a different wavelength, a plurality of second layers, and a third layer. Each of the plurality of second layers may be associated with a respective wavelength, and each of the plurality of second layers may include photonic filters tuned to their respective wavelength, a photonic modulator, and a photonic detector. The third layer may include a plurality of photonic circuits, with each of the plurality of photonic circuits associated with a respective second layer of the plurality of second layers. Additionally, each of the plurality of photonic circuits may include a photonic filter tuned to a respective wavelength associated with a respective second layer, a photonic detector and a photonic modulator.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Sion Quinlan
  • Publication number: 20070208978
    Abstract: An embodiment includes encoding digital data into encoded digital data in a transition minimized differential signaling encoder, serializing the encoded digital data into encoded and serial digital data in a serializer, generating test data in a pseudo-random binary sequence generator circuit, transmitting the encoded and serial digital data through a multiplexer to a transmission medium in a normal mode of operation, and transmitting the test data through the multiplexer to the transmission medium in a test mode of operation. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The test data may be pseudo-random binary sequence data. The digital data may include data to generate colors in a visual image, and the encoded and serial digital data may be received, deserialized, decoded, and displayed in a display unit.
    Type: Application
    Filed: February 21, 2006
    Publication date: September 6, 2007
    Inventors: Sion Quinlan, David Warner
  • Publication number: 20050221522
    Abstract: The manufacture of multi-level optical imagers and the resulting imagers are described. Multiple levels of metallization are prepared, each level having a via. The vias are aligned and a material having a higher refractive index than its surrounds is positioned within the vias to form an optical channel. The higher refractive index material may be an optical plug. A lens is mounted at one end of the optical channel and a photoconversion device is mounted at the other end.
    Type: Application
    Filed: June 3, 2005
    Publication date: October 6, 2005
    Inventor: Sion Quinlan
  • Publication number: 20050178001
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Application
    Filed: February 7, 2005
    Publication date: August 18, 2005
    Inventors: Sion Quinlan, Tim Bales
  • Publication number: 20050145976
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Application
    Filed: January 20, 2005
    Publication date: July 7, 2005
    Inventors: Sion Quinlan, Tim Bales
  • Publication number: 20050130348
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Application
    Filed: January 20, 2005
    Publication date: June 16, 2005
    Inventors: Sion Quinlan, Tim Bales
  • Publication number: 20050130346
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Application
    Filed: January 20, 2005
    Publication date: June 16, 2005
    Inventors: Sion Quinlan, Tim Bales
  • Publication number: 20050130347
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Application
    Filed: January 20, 2005
    Publication date: June 16, 2005
    Inventors: Sion Quinlan, Tim Bales
  • Publication number: 20050121754
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Application
    Filed: January 20, 2005
    Publication date: June 9, 2005
    Inventors: Sion Quinlan, Tim Bales
  • Patent number: 6885324
    Abstract: A method of testing or calibrating analog to digital converters in a digital test environment comprising: providing a phase lock loop having a voltage controlled oscillator, and calibrating the phase lock loop in terms of the relation between the input voltage to the voltage controlled oscillator and the frequency of the loop; providing in the phase lock loop a digital comparison means providing an output to a charge pumping means which provides a voltage to the input of a voltage controlled oscillator; applying a predetermined code to one input of the digital comparison means and applying the output code of an analog to digital converter to a further input of the digital comparison means, and applying the input voltage to the voltage controlled oscillator to the input of the analog to digital converter; and when equality is established between the digital codes applied to the inputs of the digital comparison means, and the frequency of the phase lock loop is constant, measuring the frequency of the phase loc
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: April 26, 2005
    Assignee: LSI Logic Corporation
    Inventor: Sion Quinlan
  • Publication number: 20050001146
    Abstract: The manufacture of multi-level optical imagers and the resulting imagers are described. Multiple levels of metallization are prepared, each level having a via. The vias are aligned and a material having a higher refractive index than its surrounds is positioned within the vias to form an optical channel. The higher refractive index material may be an optical plug. A lens is mounted at one end of the optical channel and a photoconversion device is mounted at the other end.
    Type: Application
    Filed: July 2, 2003
    Publication date: January 6, 2005
    Applicant: Micron Technology, Inc.
    Inventor: Sion Quinlan