Patents by Inventor Siou-Cyun LIN

Siou-Cyun LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11049764
    Abstract: A method for fabricating a semiconductor device comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: June 29, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jung-Che Chang, Bao-Tzeng Huang, Yu-Hong Huang, Siou-Cyun Lin
  • Publication number: 20210183695
    Abstract: A method for fabricating a semiconductor device comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 17, 2021
    Inventors: Jung-Che CHANG, Bao-Tzeng HUANG, Yu-Hong HUANG, Siou-Cyun LIN