Patents by Inventor Siqiong You

Siqiong You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7017141
    Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: March 21, 2006
    Inventors: Leigh C. Anderson, Nicolas B. Cobb, Laurence W. Grodd, Emile Sahouria, Siqiong You
  • Patent number: 6901574
    Abstract: A method of translating device layout data to a format for a mask writing tool includes the acts of reading a file defining a number of cells that represent structures on the device. One or more cells are selected and one or more modified cells based on the interaction of the selected cells with other cells in the device layout are created. One or more additional cells is created that will create structures on the mask that are not formed by writing files corresponding to the modified cells and areas that prevent extraneous structures from being formed on the mask at a selected location by the writing of the files corresponding to the modified cells. A jobdeck for the mask writing tool is created that indicates where the files corresponding to modified cells and the one or more additional cells should be written to create one or more masks or reticles.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: May 31, 2005
    Inventors: Patrick J. LaCour, Emile Sahouria, Siqiong You
  • Publication number: 20020157068
    Abstract: A method of translating device layout data to a format for a mask writing tool includes the acts of reading a file defining a number of cells that represent structures on the device. One or more cells are selected and one or more modified cells based on the interaction of the selected cells with other cells in the device layout are created. One or more additional cells is created that will create structures on the mask that are not formed by writing files corresponding to the modified cells and areas that prevent extraneous structures from being formed on the mask at a selected location by the writing of the files corresponding to the modified cells. A jobdeck for the mask writing tool is created that indicates where the files corresponding to modified cells and the one or more additional cells should be written to create one or more masks or reticles.
    Type: Application
    Filed: February 9, 2001
    Publication date: October 24, 2002
    Applicant: Mentor Graphics, an Oregon corporation
    Inventors: Patrick J. LaCour, Emile Sahouria, Siqiong You
  • Publication number: 20020100005
    Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.
    Type: Application
    Filed: March 27, 2002
    Publication date: July 25, 2002
    Applicant: Mentor Graphics Corporation
    Inventors: Leigh C. Anderson, Nicolas B. Cobb, Laurence W. Grodd, Emile Sahouria, Siqiong You
  • Patent number: 6415421
    Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: July 2, 2002
    Assignee: Mentor Graphics Corporation
    Inventors: Leigh C. Anderson, Nicolas B. Cobb, Laurence W. Grodd, Emile Sahouria, Siqiong You
  • Publication number: 20010052107
    Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.
    Type: Application
    Filed: December 22, 2000
    Publication date: December 13, 2001
    Applicant: Mentor Graphics Corporation
    Inventors: Leigh C. Anderson, Nicolas B. Cobb, Laurence W. Grodd, Emile Sahouria, Siqiong You