Patents by Inventor Sira G. Sudhindranath

Sira G. Sudhindranath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Off-grid metal layer utilization
    Patent number: 6338972
    Abstract: Routing of electrical connections between cells arranged in cell columns on an integrated circuit (IC) die. Electrical connections are routed on a routing layer between cells located in a first cell column. An identification is made of an available off-grid resource capable of being used for wire routing that is both within the first cell column and on the routing layer. An electrical connection is routed between a first cell and a second cell located in different cell columns using at least a portion of the identified available off-grid resource. Also, an integrated circuit die which includes vertical power rails and vertical ground rails. Cell columns, including a first cell column and a second cell column, are each bordered by a vertical power rail and a vertical ground rail. A channel is provided between the first cell column and the second cell column.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: January 15, 2002
    Assignee: LSI Logic Corporation
    Inventors: Sira G. Sudhindranath, Anand Sethuraman
  • Off-grid metal layer utilization
    Patent number: 6174742
    Abstract: Routing of electrical connections between cells arranged in cell columns on an integrated circuit (IC) die. Electrical connections are routed on a routing layer between cells located in a first cell column. An identification is made of an available off-grid resource capable of being used for wire routing that is both within the first cell column and on the routing layer. An electrical connection is routed between a first cell and a second cell located in different cell columns using at least a portion of the identified available off-grid resource. Also, an integrated circuit die which includes vertical power rails and vertical ground rails. Cell columns, including a first cell column and a second cell column, are each bordered by a vertical power rail and a vertical ground rail. A channel is provided between the first cell column and the second cell column.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: January 16, 2001
    Assignee: LSI Logic Corporation
    Inventors: Sira G. Sudhindranath, Anand Sethuraman