Patents by Inventor Siraj Fulum

Siraj Fulum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128979
    Abstract: In one aspect, an analog to digital converter (ADC) for a multiply-accumulator (MAC) system comprising: an ADC control that receives a VREF and generates a plurality of timing signals to an ADC, and wherein the plurality of timing signals comprises an S1 signal, an S3 signal, an S4 signal, an ECO signal, a CLOCK signal, and a COUNTER<N:0> signal; the ADC that comprises: a pre-charge system comprising a sense capacitor that stores an integrated charge IMAC over a time T and develops voltage VMAC, and wherein the S1 signal defines the pre-charge phase of the sense capacitor.
    Type: Application
    Filed: August 7, 2023
    Publication date: April 18, 2024
    Inventors: vishal sarin, Biprangshu Saha, Sankha Saha, Vikram Kowshik, Sang T. Nguyen, Siraj Fulum Mossa
  • Patent number: 11961570
    Abstract: In one aspect, a method for NOR flash cell-array programming in a neural circuit includes the step of erasing a cell array. The method includes the step of programming a set of reference cells of a reference cell array to a target reference threshold voltage (Vt_ref). The method includes the step of generating, with the reference cells, a current or voltage, reference signal. The method includes the step of using the reference signal to bias the neural cells during verification of program state of the neural cells to achieve their respective target threshold voltages (Vt_cell). The method includes the step of programming a set of neural cells of a neural cell array to their respective target threshold voltages.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 16, 2024
    Inventors: Vishal Sarin, Vikram Kowshik, Purval Sule, Siraj Fulum Mossa
  • Patent number: 11799489
    Abstract: The method provides for a low power and a temperature independent analog to digital convertor for systems which use non-volatile cells for forming neurons to be used for neural network applications. The method uses a common counter which can be an up-counter or a down-counter depending on implementation, but in which the source and sink currents to a comparator are changed with temperature by the same percentage as the average bit line current for specific weight distributions programmed in the non-volatile cells forming the neurons. The method uses charge accumulation for detecting the average neuron current.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: October 24, 2023
    Inventors: Vishal Sarin, Vikram Kowshik, Sankha Subhra Saha, Siraj Fulum
  • Publication number: 20210143828
    Abstract: The method provides for a low power and a temperature independent analog to digital convertor for systems which use non-volatile cells for forming neurons to be used for neural network applications. The method uses a common counter which can be an up-counter or a down-counter depending on implementation, but in which the source and sink currents to a comparator are changed with temperature by the same percentage as the average bit line current for specific weight distributions programmed in the non-volatile cells forming the neurons. The method uses charge accumulation for detecting the average neuron current.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 13, 2021
    Inventors: Vishal Sarin, Vikram Kowshik, Sankha Subhra Saha, Siraj Fulum
  • Publication number: 20210043264
    Abstract: In one aspect, a method for NOR flash cell-array programming in a neural circuit includes the step of erasing a cell array. The method includes the step of programming a set of reference cells of a reference cell array to a target reference threshold voltage (Vt_ref). The method includes the step of generating, with the reference cells, a current or voltage, reference signal. The method includes the step of using the reference signal to bias the neural cells during verification of program state of the neural cells to achieve their respective target threshold voltages (Vt_cell). The method includes the step of programming a set of neural cells of a neural cell array to their respective target threshold voltages.
    Type: Application
    Filed: June 25, 2020
    Publication date: February 11, 2021
    Inventors: Vishal Sarin, Vikram Kowshik, Purval Sule, Siraj Fulum Mossa