Patents by Inventor Sireesha Gogineni
Sireesha Gogineni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881441Abstract: Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.Type: GrantFiled: September 29, 2017Date of Patent: January 23, 2024Assignee: Intel CorporationInventors: Sireesha Gogineni, Andrew Kim, Yong She, Karissa J. Blue
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Patent number: 11848292Abstract: Embodiments described herein provide techniques for forming an interconnect structure that includes micro features formed therein. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a metal pad over a substrate (e.g., a semiconductor package, a PCB, an interposer, etc.). Micro features may be formed in an edge of the metal pad or away from the edge of the metal pad. The micro features can assist with: (i) increasing the contact area between solder used to form an interconnect joint and the metal pad; and (ii) improving adherence of solder used to form an interconnect joint to the metal pad. These benefits can improve interconnect joint reliability by, among others, improving the interconnect joint's ability to absorb stress from substrates having differing coefficients of thermal expansion.Type: GrantFiled: October 11, 2018Date of Patent: December 19, 2023Assignee: Intel CorporationInventors: Sireesha Gogineni, Yi Xu, Yuhong Cai
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Patent number: 11694976Abstract: Embodiments described herein provide techniques for forming an interconnect structure that includes a bowl shaped pad. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a substrate (e.g., a semiconductor package, a PCB, etc.); and a metal pad over the substrate. The metal pad has a center region and an edge region. A thickness of the center region is smaller than a thickness of the edge region. A thickness of the center region may be non-uniform. The center region may have a bowl shape characterized by a stepped profile. The stepped profile is formed from metal layers arranged as steps. Alternatively, or additionally, the center region may have a bowl shape characterized by a curved profile. A pattern may be formed on or in a surface of the metal pad.Type: GrantFiled: October 11, 2018Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Yuhong Cai, Sireesha Gogineni, Yi Xu
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Publication number: 20220254757Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 18, 2022Publication date: August 11, 2022Inventors: Mao Guo, Hyoung Il Kim, Yong She, Sireesha Gogineni
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Patent number: 11393788Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.Type: GrantFiled: September 22, 2016Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Mao Guo, Hyoung Il Kim, Yong She, Sireesha Gogineni
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Publication number: 20210280558Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass , and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 22, 2016Publication date: September 9, 2021Inventors: Mao Guo, Hyoung Il Kim, Yong She, Sireesha Gogineni
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Publication number: 20200350227Abstract: Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.Type: ApplicationFiled: September 29, 2017Publication date: November 5, 2020Applicant: Intel CorporationInventors: Sireesha Gogineni, Andrew Kim, Yong She, Karissa J. Blue
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Publication number: 20200118955Abstract: Embodiments described herein provide techniques for forming an interconnect structure that includes micro features formed therein. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a metal pad over a substrate (e.g., a semiconductor package, a PCB, an interposer, etc.). Micro features may be formed in an edge of the metal pad or away from the edge of the metal pad. The micro features can assist with: (i) increasing the contact area between solder used to form an interconnect joint and the metal pad; and (ii) improving adherence of solder used to form an interconnect joint to the metal pad. These benefits can improve interconnect joint reliability by, among others, improving the interconnect joint's ability to absorb stress from substrates having differing coefficients of thermal expansion.Type: ApplicationFiled: October 11, 2018Publication date: April 16, 2020Inventors: Sireesha GOGINENI, Yi XU, Yuhong CAI
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Publication number: 20200118954Abstract: Embodiments described herein provide techniques for forming an interconnect structure that includes a bowl shaped pad. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a substrate (e.g., a semiconductor package, a PCB, etc.); and a metal pad over the substrate. The metal pad has a center region and an edge region. A thickness of the center region is smaller than a thickness of the edge region. A thickness of the center region may be non-uniform. The center region may have a bowl shape characterized by a stepped profile. The stepped profile is formed from metal layers arranged as steps. Alternatively, or additionally, the center region may have a bowl shape characterized by a curved profile. A pattern may be formed on or in a surface of the metal pad.Type: ApplicationFiled: October 11, 2018Publication date: April 16, 2020Inventors: Yuhong CAI, Sireesha GOGINENI, YI XU
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Patent number: 10490516Abstract: Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.Type: GrantFiled: January 12, 2018Date of Patent: November 26, 2019Assignee: Intel CorporationInventors: John G. Meyers, Bilal Khalaf, Sireesha Gogineni, Brian J. Long
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Publication number: 20180323172Abstract: A package with improved solder joint reliability is disclosed. The package includes dummy beams with less rigidity and stiffness (relative to the die) that are placed in between the die and the substrate. The reduced rigidity and stiffness of the dummy beams significantly mitigates any die shadow effects on the solder joints. Also, because the die is attached to the dummy beams and does not directly contact the substrate itself, the die shadow effect from a rigid die is further reduced.Type: ApplicationFiled: December 22, 2015Publication date: November 8, 2018Inventors: Mao GUO, Sireesha GOGINENI
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Publication number: 20180190776Abstract: Various embodiments disclosed relate to a semiconductor package. The semiconductor package includes a substrate having first and second opposed major surfaces. The substrate further includes a cavity having a first end defined by a portion of the first major surface and a second end defined by a portion of the second major surface. The semiconductor package further includes a first electronic component attached to the first major surface. The first electronic component substantially covers the first end of the cavity. A second electronic component is at least partially disposed within the cavity.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Sireesha Gogineni, Juan Eduardo Dominguez
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Publication number: 20180138133Abstract: Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.Type: ApplicationFiled: January 12, 2018Publication date: May 17, 2018Inventors: John G. Meyers, Bilal Khalaf, Sireesha Gogineni, Brian J. Long
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Patent number: 9871007Abstract: Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.Type: GrantFiled: September 25, 2015Date of Patent: January 16, 2018Assignee: Intel CorporationInventors: John G. Meyers, Bilal Khalaf, Sireesha Gogineni, Brian J. Long
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Publication number: 20170186701Abstract: Crack resistant electronic device package substrate technology is disclosed. In an example, an electronic device package substrate can include a substrate core material having a surface. The substrate can also include a solder ball pad coupled to the surface of the substrate. In addition, the substrate can include a layer of solder resist material coupled to the surface of the substrate at a location that leaves a gap in between a lateral side of the solder ball pad and the solder resist material.Type: ApplicationFiled: December 26, 2015Publication date: June 29, 2017Applicant: Intel CorporationInventors: Yuhong Cai, Sireesha Gogineni, John Yap
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Publication number: 20170092602Abstract: Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: John G. Meyers, Bilal Khalaf, Sireesha Gogineni, Brian J. Long