Abstract: There is described a processing register particularly adapted for use in digital processing systems to implement various digital functions as high order digital filters and other structures which presently require complicated integrated circuit arrangements.The processing register operates in five modes which are a shift register mode with multiple fixed delays, a shift register with multiple fixed delays and a time slot interchanger, a shift register mode with an alternating word pair interchanger, a programmable delay shift register and as a discrete fourier transform preprocessing module.The processing register is particularly adaptable to operate with a high speed multiplier to implement various digital processing functions. In order to accommodate mode operation the processing register contains a main shift register and a computation register which are under the control of a control register which register accepts a control input word having bits thereof indicative of a particular mode of operation.