Abstract: An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to determine that a packet needs a timestamp, determine an initial timestamp for a reference block, communicate the reference block to a monitor engine, receive an asynchronous pulse from the monitor engine after the monitor engine received the reference block, determine a synchronization timestamp for the asynchronous pulse, and determine the timestamp for the packet based on the initial timestamp for the reference block and the synchronization timestamp for the asynchronous pulse.

Abstract: Electronic devices coupled to a network may exchange messages containing time-of-day information synchronization of the internal clocks. The information exchanged may include the instant at which a message leaves the electronic device. Discussed herein are methods and systems that allow 1-step timestamping of messages containing time-of-day information. The 1-step timestamping methods and systems may reduce the impact of non-deterministic time delays in the transmit path (e.g., encryption, expansion, inclusion of tags), and may improve the accuracy of the time-of-day information of the packets. For example, systems and methods may allow accurate 1-step timestamping of IEEE 1588 Precision Time Protocol packets with the uncertainty of delays from MACSec encryption or other security mechanisms. Some embodiments employ estimation non-deterministic delay of previously transmitted packets to estimate the state of the transmit path.

Abstract: Devices and methods of providing drivers for software and hardware systems to avoid additional polling or interrupt mechanisms are provided. An electronic device includes a processor supporting a device driver to perform a data packet receiving operation or data packet transmission operation. The device driver causes the processor to receive one or more data packets to a port of the processor according to a time-synchronization protocol. The device driver polls the DMA feature for a completion status of the storing. The device driver causes the processor to determine a timestamp of the one or more data packets and to complete the data packet receiving operation without the device driver causing the processor to perform a polling operation or an interrupt operation to retrieve the timestamp of the one or more data packets.

Abstract: Devices and methods of providing drivers for software and hardware systems to avoid additional polling or interrupt mechanisms are provided. An electronic device includes a processor supporting a device driver to perform a data packet receiving operation or data packet transmission operation. The device driver causes the processor to receive one or more data packets to a port of the processor according to a time-synchronization protocol. The device driver polls the DMA feature for a completion status of the storing. The device driver causes the processor to determine a timestamp of the one or more data packets and to complete the data packet receiving operation without the device driver causing the processor to perform a polling operation or an interrupt operation to retrieve the timestamp of the one or more data packets.

Abstract: An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.

Abstract: Devices and methods of providing drivers for software and hardware systems to avoid additional polling or interrupt mechanisms are provided. An electronic device includes a processor supporting a device driver to perform a data packet receiving operation or data packet transmission operation. The device driver causes the processor to receive one or more data packets to a port of the processor according to a time-synchronization protocol. The device driver polls the DMA feature for a completion status of the storing. The device driver causes the processor to determine a timestamp of the one or more data packets and to complete the data packet receiving operation without the device driver causing the processor to perform a polling operation or an interrupt operation to retrieve the timestamp of the one or more data packets.

Abstract: Devices and methods to design and use network interfaces compliant with time-synchronization protocols via a multi-tier architecture are provided. This architecture allows for independent development between circuitry related to the time-synchronization protocols and circuitry responsible for channel access, reducing redundancies in the design process.

Abstract: Electronic devices coupled to a network may exchange messages containing time-of-day information synchronization of the internal clocks. The information exchanged may include the instant at which a message leaves the electronic device. Discussed herein are methods and systems that allow 1-step timestamping of messages containing time-of-day information. The 1-step timestamping methods and systems may reduce the impact of non-deterministic time delays in the transmit path (e.g., encryption, expansion, inclusion of tags), and may improve the accuracy of the time-of-day information of the packets. For example, systems and methods may allow accurate 1-step timestamping of IEEE 1588 Precision Time Protocol packets with the uncertainty of delays from MACSec encryption or other security mechanisms. Some embodiments employ estimation non-deterministic delay of previously transmitted packets to estimate the state of the transmit path.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to determine that a packet needs a timestamp, determine an initial timestamp for a reference block, communicate the reference block to a monitor engine, receive an asynchronous pulse from the monitor engine after the monitor engine received the reference block, determine a synchronization timestamp for the asynchronous pulse, and determine the timestamp for the packet based on the initial timestamp for the reference block and the synchronization timestamp for the asynchronous pulse.