Abstract: A storage controller includes a plurality of pipeline stages configured to process data. A system clock signal is received that has a system frequency and at least one performance metric is determined for one or more pipeline stages of the plurality of pipeline stages. A first clock signal is generated having a first frequency for operation of a first pipeline stage of the plurality of pipeline stages. Based at least in part on the at least one determined performance metric, a second clock signal is generated having a second frequency for operation of a second pipeline stage of the plurality of pipeline stages. The second frequency is less than the system frequency and may also differ from the first frequency.

Abstract: A storage controller includes a plurality of pipeline stages configured to process data. A system clock signal is received that has a system frequency and at least one performance metric is determined for one or more pipeline stages of the plurality of pipeline stages. A first clock signal is generated having a first frequency for operation of a first pipeline stage of the plurality of pipeline stages. Based at least in part on the at least one determined performance metric, a second clock signal is generated having a second frequency for operation of a second pipeline stage of the plurality of pipeline stages. The second frequency is less than the system frequency and may also differ from the first frequency.

Abstract: Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

Abstract: Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

Abstract: Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

Abstract: Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

Abstract: An apparatus includes a circuit and a voltage regulator having a first output terminal that is coupled to provide electrical power to the circuit. The voltage regulator is configured to provide the electrical power in a supply voltage range. The voltage regulator has a second output terminal configured to provide an indicator of electrical current provided by the first output terminal for control of the circuit.

Abstract: Systems and methods to share a plurality of virtual network interface controllers (vNICs) amongst a plurality of hosts 104 are described. The described methods are implemented in a network sharing system (NISS) (102) including a programmable vNIC cluster (204) comprising the plurality of vNICs, where a set of vNICs from amongst the plurality of vNICs is dynamically configured to communicate with a host (104-1) from amongst the plurality of hosts (104). Further, the NISS (102) includes a multi-host peripheral component interconnect (PCI) express (PCIe) interface and mapper (MHIP) (202) coupled to the programmable vNIC cluster (204), to receive data packets from the set of vNICs, wherein the set of vNICs comprises one or more vNICs; and provide the data packets from the set of vNICs to the host (104-1) based on demultiplexing of the data packets.

Abstract: Described herein is a system having a multi-host Ethernet controller (102) configured to provide communication and control between two or more independent host processors (104) and a network device. In one implementation, the multi host Ethernet controller (102), having an integrated L2 switch (110) to enable a plurality of independent host systems to access same physical gigabit network port concurrently. Each host processor (104) sees the controller as PCI based independent network controller and accesses the controller using its own mini-port driver. The common programming parameters such as Link Speed or Inter Packet Gap (IPG) are programmed by a virtualization engine. Packets from network (LAN) are switched based on MAC destination address and sent to corresponding host based on MAC destination address. Packets from each host processor (104) are forwarded to network interface or other host processor (104) based on MAC destination address.

Abstract: Systems and methods to share a plurality of virtual network interface controllers (vNICs) amongst a plurality of hosts 104 are described. The described methods are implemented in a network sharing system (NISS) (102) including a programmable vNIC cluster (204) comprising the plurality of vNICs, where a set of vNICs from amongst the plurality of vNICs is dynamically configured to communicate with a host (104-1) from amongst the plurality of hosts (104). Further, the NISS (102) includes a multi-host peripheral component interconnect (PCI) express (PCIe) interface and mapper (MHIP) (202) coupled to the programmable vNIC cluster (204), to receive data packets from the set of vNICs, wherein the set of vNICs comprises one or more vNICs; and provide the data packets from the set of vNICs to the host (104-1) based on demultiplexing of the data packets.

Abstract: Described herein is a system having a multi-host Ethernet controller (102) configured to provide communication and control between two or more independent host processors (104) and a network device. In one implementation, the multi host Ethernet controller (102), having an integrated L2 switch (110) to enable a plurality of independent host systems to access same physical gigabit network port concurrently. Each host processor (104) sees the controller as PCI based independent network controller and accesses the controller using its own mini-port driver. The common programming parameters such as Link Speed or Inter Packet Gap (IPG) are programmed by a virtualization engine. Packets from network (LAN) are switched based on MAC destination address and sent to corresponding host based on MAC destination address. Packets from each host processor (104) are forwarded to network interface or other host processor (104) based on MAC destination address.