Patents by Inventor Sitaraman Iyer

Sitaraman Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10795841
    Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren Jue, Sitaraman Iyer
  • Publication number: 20190391945
    Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.
    Type: Application
    Filed: February 25, 2019
    Publication date: December 26, 2019
    Applicant: Intel Corporation
    Inventors: Venkatraman Iyer, Darren Jue, Sitaraman Iyer
  • Patent number: 9965370
    Abstract: A port of a first device includes remote device detection logic to detect, on a link, a remote second device, determine, from a voltage generated at the port, whether the second device is direct current (DC)-coupled or alternating current (AC)-coupled to the link, and select one of first settings or second settings to be applied at the port in communications over the link with the second device based on whether the second device is DC-coupled or AC-coupled.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: May 8, 2018
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Zuoguo Wu, Jeffrey Ou, Sitaraman Iyer
  • Publication number: 20170185502
    Abstract: A port of a first device includes remote device detection logic to detect, on a link, a remote second device, determine, from a voltage generated at the port, whether the second device is direct current (DC)-coupled or alternating current (AC)-coupled to the link, and select one of first settings or second settings to be applied at the port in communications over the link with the second device based on whether the second device is DC-coupled or AC-coupled.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Inventors: Venkatraman Iyer, Zuoguo Wu, Jeffrey Ou, Sitaraman Iyer
  • Patent number: 9612986
    Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Sitaraman Iyer