Patents by Inventor Sitta Jewjaitham

Sitta Jewjaitham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7153724
    Abstract: A series of grooves are etched in a leadframe to be used in fabricating a group of semiconductor packages at locations where the leadframe will later be sawed to separate the semiconductor packages. In variations of the process, the grooves may be wider or narrower than the kerf of the saw cuts and may be formed on the side of the leadframe facing towards or away from the entry of the saw blade.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: December 26, 2006
    Assignee: NS Electronics Bangkok (1993) Ltd.
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai, Sitta Jewjaitham, Yee Heong Chua
  • Patent number: 7060535
    Abstract: A flat no-lead semiconductor die package contains a plurality of studs that protrude from the bottom surface of the capsule and act as electrical contacts, allowing the package to be mounted on a flat surface such as a printed circuit board, while permitting external circuit to be located on the flat surface directly beneath the package. The package may or may not contain a die-attach pad. The die may be mounted flip-chip style on the stud contacts and die-attach pad. A method of fabricating the package includes etching an upper portion of a metal sheet through a mask layer, attaching dice at locations on the surface of the metal sheet, forming a layer of molding compound over the dice, etching the lower portion of the metal sheet through a second mask layer, and separating the packages with a dicing saw or punch tool.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: June 13, 2006
    Assignee: NS Electronics Bangkok (1993) Ltd.
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai, Sitta Jewjaitham