Abstract: A method, system and product for directing verification towards bug-prone portions. The method comprising syntactically analyzing a computer program to identify portions of the computer program that correspond to one or more bug patterns; and performing verification of the computer program, wherein the verification comprises traversing a control flow graph of the computer program and tracking symbolic values of variables of the computer program, wherein said performing comprises directing the traversal of the control flow graph to nodes of the control flow graph that correspond to the identified portions, whereby bug-prone portions of the computer program are prioritized to be verified before non-bug-prone portions of the computer program.

Abstract: A method of applying formal verification methodologies to event processing applications is provided herein.

Abstract: A method, system and product for directing verification towards bug-prone portions. The method comprising syntactically analyzing a computer program to identify portions of the computer program that correspond to one or more bug patterns; and performing verification of the computer program, wherein the verification comprises traversing a control flow graph of the computer program and tracking symbolic values of variables of the computer program, wherein said performing comprises directing the traversal of the control flow graph to nodes of the control flow graph that correspond to the identified portions, whereby bug-prone portions of the computer program are prioritized to be verified before non-bug-prone portions of the computer program.

Abstract: A method, apparatus, and product for avoiding similar counter-examples in model checking. One method comprises model checking of a program by traversing control flow paths of the program to determine states associated with execution of the program, each state comprises at least symbolic values of variables; said traversing is biased to give preference to traversing control flow paths that are substantially different than control flow paths associated with traces of the program; whereby said model checking is guided away from executions that are similar to the traces. A second method comprises obtaining a counter-example produced by a model checker, computing a distance between a control flow path of the counter-example and between a set of one or more control flow paths of additional counter-examples; and in response to the distance being below a threshold, dropping the counter-example.

Abstract: A method, apparatus and product for dominant state based coverage metric. The method comprising: determining whether all possible states of a computer program were examined based on an analysis of states that were examined excluding controlled states that are dominated by a self-dominating states; wherein the controlled states are associated with a controlled nodes in a control flow graph of the computer program, wherein the self-dominating states are associated with a self-dominating node in the control flow graph; wherein each execution path in the control flow graph that reaches the controlled nodes also includes the self-dominating node; and wherein there exists an execution path in the control flow graph that both starts and ends at the self-dominating node and further includes at least one controlled node.

Abstract: A method, apparatus and product for dominant state based coverage metric. The method comprising: determining whether all possible states of a computer program were examined based on an analysis of states that were examined excluding controlled states that are dominated by a self-dominating states; wherein the controlled states are associated with a controlled nodes in a control flow graph of the computer program, wherein the self-dominating states are associated with a self-dominating node in the control flow graph; wherein each execution path in the control flow graph that reaches the controlled nodes also includes the self-dominating node; and wherein there exists an execution path in the control flow graph that both starts and ends at the self-dominating node and further includes at least one controlled node.

Abstract: A computer implemented method, an computerized apparatus and a computer program product for validating revised computer programs. The method performed by a computerized device, comprising: validating a computer program having one or more revised instructions, wherein said validating comprises: checking the computer program with respect to only a portion of a Control Flow Graph (CFG) of the computer program, wherein the portion of the CFG including all paths of the CFG that include at least one node associated with a revised instruction.

Abstract: A computerized system comprising: a processor; a first interface configured to obtain a constraint; a second interface configured to obtain a first model, wherein the first model is configured to be utilized in model checking, and the first model, when constrained by the constraint, comprises at least one finite path; and a finite path removal module implemented in the processor and configured to generate a second model equivalent to the first model obtained by said second interface, wherein the second model excludes a portion of the at least one finite path, and the second model is configured to be utilized in model checking.

Abstract: A method of applying formal verification methodologies to event processing applications is provided herein.

Abstract: A computer-implemented method for verifying a design includes representing a verification directive, which pertains to the design and includes a local variable, by a finite state machine. The state machine includes multiple states, with transitions among the states, transition conditions associated with the transitions, and procedural blocks, which correspond to the transitions and define operations to be performed on the local variable when traversing the respective transitions. The finite state machine is executed by traversing the transitions in accordance with the respective transition conditions and modifying the local variable in accordance with the respective procedural blocks of the traversed transitions, so as to verify the design with respect to the verification directive.

Abstract: A model may comprise finite paths in respect to a constraint. The model and the constraint may be modified such that a portion of the limitations induces by the constraint is injected to the model. Adding the limitation directly to the model may be expressed by a reduction of a measurement of nondeterminism in the model. The model may be modified based on the constraint, and the constraint may be modified based on the model. The constraint may be strengthened to provide for an early finite path detection.

Abstract: Device, system and method of efficient automata-based implementation of liveness properties for formal verification. A system according to embodiments of the invention includes a property transformation module to receive an assume verification directive on a liveness property in a property specification language, and to translate the property a fairness statement that uses a deterministic automaton. The deterministic automaton is exponential in the size of the input property. The assume verification directive may be transformed into a strong suffix implication in the property specification language.

Abstract: A computer-implemented method for verifying a design includes representing a verification directive, which pertains to the design and includes a local variable, by a finite state machine. The state machine includes multiple states, with transitions among the states, transition conditions associated with the transitions, and procedural blocks, which correspond to the transitions and define operations to be performed on the local variable when traversing the respective transitions. The finite state machine is executed by traversing the transitions in accordance with the respective transition conditions and modifying the local variable in accordance with the respective procedural blocks of the traversed transitions, so as to verify the design with respect to the verification directive.

Abstract: Device, system and method of efficient automata-based implementation of liveness properties for formal verification. A system according to embodiments of the invention includes a property transformation module to receive an assume verification directive on a liveness property in a property specification language, and to translate the property a fairness statement that uses a deterministic automaton. The deterministic automaton is exponential in the size of the input property. The assume verification directive may be transformed into a strong suffix implication in the property specification language.