Abstract: A computer system having a processor and at least one peripheral has a programmable shared memory system and method that selectively dedicates a first potion of memory to use by the processor and allocates a second portion of memory to shared use by the processor and any peripherals in the system. The programmable memory architecture is implemented using a dual bus architecture having a first-bus connected to the processor and a second bus coupled to the processor by a system controller and to the peripherals by a peripheral controller. The programmable memory architecture additionally has a configuration controller coupled to each configurable memory bank in the system. Each configuration controller is additionally coupled to both the first and second buses. Under programmed control, the each configuration controller couples the associated memory to either the first or second bus, responsive to configuration information stored in the system controller.