Patents by Inventor Siu-Weng Simon Wong

Siu-Weng Simon Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10079438
    Abstract: A radio-frequency power receiving device has RF antennas connected to multiple controllable rectifying circuits to produce corresponding DC signals which are combined in a controllable switching network to produce a combined DC output. A control unit determines an amplitude control signal that controls each rectifying circuit and also determines switch control signals that control a switching network. The switching network controllably combines the direct-current signals to combine the multiple corresponding direct-current signals in series, in parallel, or in a combination of series and parallel.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: September 18, 2018
    Assignee: NVoLogic Inc
    Inventors: Yuji Tanabe, Ada Shuk Yan Poon, Siu-Weng Simon Wong
  • Publication number: 20180083371
    Abstract: A radio-frequency power receiving device has RF antennas connected to multiple controllable rectifying circuits to produce corresponding DC signals which are combined in a controllable switching network to produce a combined DC output. A control unit determines an amplitude control signal that controls each rectifying circuit and also determines switch control signals that control a switching network. The switching network controllably combines the direct-current signals to combine the multiple corresponding direct-current signals in series, in parallel, or in a combination of series and parallel.
    Type: Application
    Filed: September 21, 2016
    Publication date: March 22, 2018
    Inventors: Yuji Tanabe, Ada Shuk Yan Poon, Siu-Weng Simon Wong
  • Patent number: 6756834
    Abstract: ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O's through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only one ESD clamp rather than two ESD-protection devices must turn on. The ESD clamps and ESD-protection devices can be gate-coupled n-channel transistors with coupling capacitors between the pad and the transistor gate. Devices can also be substrate-triggered transistors or active ESD clamps that include an inverter between a coupling capacitor to the CDL and the n-channel transistor gate.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: June 29, 2004
    Assignee: Pericom Semiconductor Corp.
    Inventors: Paul C. F. Tong, Siu-Weng Simon Wong, Ping Ping Xu, Zhi Qing Liu, Wensong Chen
  • Patent number: 6597227
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: July 22, 2003
    Assignee: Atheros Communications, Inc.
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
  • Patent number: 6593794
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: July 15, 2003
    Assignee: Atheros Communications
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
  • Patent number: 6509779
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: January 21, 2003
    Assignee: Atheros Communications, Inc.
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
  • Publication number: 20020125931
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Application
    Filed: February 7, 2002
    Publication date: September 12, 2002
    Applicant: ATHEROS COMMUNICATIONS, INC.
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
  • Publication number: 20020121924
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Application
    Filed: February 7, 2002
    Publication date: September 5, 2002
    Applicant: ATHEROS COMMUNICATIONS, INC.
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland