Patents by Inventor Siva Kothamasu

Siva Kothamasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT WITH LOW POWER MODE MANAGEMENT
    Publication number: 20250015698
    Abstract: In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.
    Type: Application
    Filed: September 26, 2024
    Publication date: January 9, 2025
    Inventors: Venkateswar Kowkutla, Kazunobu Shin, Venkateswara Pothireddy, Siva Kothamasu, John Apostol, Raghavendra Santhanagopal, Rajagopal Kollengode Ananthanarayanan, Rejitha Nair, Charles Gerlach, Ravi Teja Reddy
  • Integrated circuit with low power mode management
    Patent number: 12132386
    Abstract: In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: October 29, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Venkateswar Kowkutla, Kazunobu Shin, Venkateswara Pothireddy, Siva Kothamasu, John Apostol, Raghavendra Santhanagopal, Rajagopal Kollengode Ananthanarayanan, Rejitha Nair, Charles Gerlach, Ravi Teja Reddy
  • INTEGRATED CIRCUIT WITH LOW POWER MODE MANAGEMENT
    Publication number: 20230238872
    Abstract: In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.
    Type: Application
    Filed: January 27, 2023
    Publication date: July 27, 2023
    Inventors: Venkateswar Kowkutla, Kazunobu Shin, Venkateswara Pothireddy, Siva Kothamasu, John Apostol, Raghavendra Santhanagopal, Rajagopal Kollengode Ananthanarayanan, Rejitha Nair, Charles Gerlach, Ravi Teja Reddy