Patents by Inventor SIVA KUMAR LANKA

SIVA KUMAR LANKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055832
    Abstract: A VCSEL array comprises a plurality of non-isolated VCSEL emitters. Each non-isolated VCSEL emitter comprises a first reflector region, a current confining oxide layer, an oxide aperture, an active region, and a second reflector region. The current confining oxide layer and oxide aperture are made by oxidizing a relatively high Al-content layer via separate oxidation holes. The separate oxidation holes surround the oxide aperture. The first reflector regions of the plurality of non-isolated VCSEL structures are connected such that they are not isolated from each other completely by any isolation structure, and the second reflector regions of the plurality of non-isolated VCSEL structures are connected such that they are not isolated from each other completely by any isolation structure.
    Type: Application
    Filed: February 24, 2020
    Publication date: February 15, 2024
    Applicant: Shenzhen Raysees AI Technology Co., Ltd.
    Inventors: Dongseok Kang, Yongxiang He, SIVA KUMAR LANKA, Yang Wang
  • Publication number: 20230130341
    Abstract: A bottom-emitting multijunction VCSEL array includes a first reflector region, a multijunction active region, and a second reflector region. In one aspect, the multijunction VCSEL array is attached to a submount by flip-chip bonding. In another aspect, the multijunction VCSEL array further includes a contact layer formed between the first reflector region and the substrate. The multijunction VCSEL array is attached to a submount by flip-chip bonding.
    Type: Application
    Filed: May 22, 2020
    Publication date: April 27, 2023
    Applicant: SHENZHEN RAYSEES AI TECHNOLOGY Co. Ltd.
    Inventors: Dongseok Kang, Siva Kumar Lanka, Yongxiang He, Yang Wang
  • Publication number: 20230128994
    Abstract: A VCSEL array comprises series-connected VCSEL sub-arrays formed on a single chip. The VCSEL sub-arrays each comprises VCSEL emitters fabricated on a semi-insulating layer. A common cathode contact of a VCSEL sub-array is electrically connected to a common anode contact of a neighboring VCSEL sub-array. To reduce leakage, the bandgap energy level of the semi-insulating layer is higher than the photon energy of the output beam. In one embodiment, the semi-insulating layer is grown on a conductive layer. A common cathode contact of the last VCSEL sub-array in a series is electrically connected to the conductive layer. In another embodiment, multiple wire-bonding areas are electrically connected to common anode contacts of multiple VCSEL sub-arrays respectively. The wire-bonding areas provide different input impedance options for a VCSEL array.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 27, 2023
    Applicant: Raysees Technology (Shenzhen) Co. Ltd.
    Inventors: Dongseok Kang, Yongxiang He, SIVA KUMAR LANKA, Yang Wang