Abstract: An illustrative embodiment disclosed is a circuit including an edge-triggered flip-flop having a first input port, a first clock port, and a first output port. The edge-triggered flip-flop receives, at the first clock port, a strobe having a first edge and a second edge. The edge-triggered flip-flop receives, at the first input port, a control byte time-aligned with the first edge and a data byte time-aligned with the second edge. The edge-triggered flip-flop passes, to the first output port, the control byte based on the first edge and the data byte based on the second edge. The circuit includes an inputs/outputs (I/O) decoder coupled to the first output port. The I/O decoder sends the control byte to microcontroller and sends the data byte to memory cells.

Abstract: An Intelligent Sensor Interfacing Unit (ISIU) for detection and configuration of sensors for a Portable Electronic Device (PED). The ISIU may identify sensors connected to the PED, according to an implementation of the present subject matter. The ISIU then determines information relating to the capabilities and requirements of the identified sensors. The ISIU on the basis of the determined sensor information may access that one of the sensors' identified may be newly coupled to the PED. Further, the ISIU upon accessing that one of the sensors' may be newly coupled to the PED, shares sensor information with Host CPU of the PED. The Host CPU upon receiving such information configures the newly coupled sensor and trains the ISIU for execution of the newly coupled sensor in future.

Abstract: Described herein is a virtualized storage system (VSS), for sharing a storage cluster comprising a plurality of storage devices, among multiple hosts. The virtualized storage system comprises a plurality of virtual host bus adapters (vHBA), wherein each vHBA is connected to a host, though a standard based host bus interface. The VSS further comprises a storage fabric switch for connecting the plurality of the vHBAs with the storage cluster through a cluster of storage controllers to facilitate transfer of data and commands between the hosts and the storage devices, wherein the storage fabric switch provide storage services for each host, the storage services comprising at least one of backup, replication and thin-provisioning. The storage fabric switch further comprises a command processing engine (CPE) to map commands received from the plurality of vHBAs, in a virtual addressing domain, to a physical address of a mapped storage controller for execution.

Abstract: An Intelligent Sensor Interfacing Unit (ISIU) for detection and configuration of sensors for a Portable Electronic Device (PED). The ISIU may identify sensors connected to the PED, according to an implementation of the present subject matter. The ISIU then determines information relating to the capabilities and requirements of the identified sensors. The ISIU on the basis of the determined sensor information may access that one of the sensors' identified may be newly coupled to the PED. Further, the ISIU upon accessing that one of the sensors' may be newly coupled to the PED, shares sensor information with Host CPU of the PED. The Host CPU upon receiving such information configures the newly coupled sensor and trains the ISIU for execution of the newly coupled sensor in future.

Abstract: Described herein is a virtualized storage system (VSS), for sharing a storage cluster comprising a plurality of storage devices, among multiple hosts. The virtualized storage system comprises a plurality of virtual host bus adapters (vHBA), wherein each vHBA is connected to a host, though a standard based host bus interface. The VSS further comprises a storage fabric switch for connecting the plurality of the vHBAs with the storage cluster through a cluster of storage controllers to facilitate transfer of data and commands between the hosts and the storage devices, wherein the storage fabric switch provide storage services for each host, the storage services comprising at least one of backup, replication and thin-provisioning. The storage fabric switch further comprises a command processing engine (CPE) to map commands received from the plurality of vHBAs, in a virtual addressing domain, to a physical address of a mapped storage controller for execution.

Abstract: Described herein is a system (102) having a virtualization and switching system configured to virtualize I/O devices (108) and perform switching of the I/O devices (108) and I/O requests. The virtualization and switching system (102) includes a peripheral virtualization controller (PVC) (204), at least one device control module (206) connected to the PVC (204), and at least one command parser (210). The PVC (204) is configured to manage I/O virtualization and I/O command access of different I/O devices (108). The device control module (206) is configured to store configuration and I/O device registers, implemented by the PVC (204) to enable virtualization of I/O devices (108). The device control module (206) also implements the I/O command and switching logic to perform graceful handling of the I/O commands and virtualized I/O devices between multiple host processors (104).

Abstract: Disclosed herein is a system having a multi-processor configuration for electronics devices and systems, such as, computing and communication devices like laptop, notebook, tablets, smartphones, etc. In accordance with one embodiment of the subject matter the system comprises a plurality of processors and a multi protocol multi-root input output virtualization (MPMRIOV) switch communicatively coupled to at least one of the plurality of processors. The system further includes a peripheral and interface virtualization unit (PIVU) coupled to the MPMRIOV switch. In said embodiment, the PIVU is configured to communicatively couple at least one of the plurality of processors with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral, and a non PCIe compliant peripheral.

Abstract: Described herein is a system (102) having a virtualization and switching system configured to virtualize I/O devices (108) and perform switching of the I/O devices (108) and I/O requests. The virtualization and switching system (102) includes a peripheral virtualization controller (PVC) (204), at least one device control module (206) connected to the PVC (204), and at least one command parser (210). The PVC (204) is configured to manage I/O virtualization and I/O command access of different I/O devices (108). The device control module (206) is configured to store configuration and I/O device registers, implemented by the PVC (204) to enable virtualization of I/O devices (108). The device control module (206) also implements the I/O command and switching logic to perform graceful handling of the I/O commands and virtualized I/O devices between multiple host processors (104).

Abstract: Disclosed herein is a system having a multi-processor configuration for electronics devices and systems, such as, computing and communication devices like laptop, notebook, tablets, smartphones, etc. In accordance with one embodiment of the subject matter the system comprises a plurality of processors and a multi protocol multi-root input output virtualization (MPMRIOV) switch communicatively coupled to at least one of the plurality of processors. The system further includes a peripheral and interface virtualization unit (PIVU) coupled to the MPMRIOV switch. In said embodiment, the PIVU is configured to communicatively couple at least one of the plurality of processors with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral, and a non PCIe compliant peripheral.

Abstract: An integrated circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices.

Abstract: An integrated circuit suitable for power conservation is disclosed. The circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices.