Patents by Inventor Siva Ramakrishnan

Siva Ramakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synchronizing memory copy operations with memory accesses
    Patent number: 7257682
    Abstract: In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: August 14, 2007
    Assignee: Intel Corporation
    Inventors: Siva Ramakrishnan, Ioannis Schoinas
  • Synchronizing memory copy operations with memory accesses
    Publication number: 20060242367
    Abstract: In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.
    Type: Application
    Filed: June 22, 2006
    Publication date: October 26, 2006
    Inventors: Siva Ramakrishnan, Ioannis Schoinas
  • Performing memory RAS operations over a point-to-point interconnect
    Patent number: 7127567
    Abstract: In some embodiments, a memory transaction is received that was sent over an unordered interconnect. A determination is made as to whether an address conflict exists between the memory transaction and another memory transaction. If the address conflict exists the memory transaction is forwarded only after waiting until the conflict is resolved. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Siva Ramakrishnan, Ioannis Schoinas
  • Synchronizing memory copy operations with memory accesses
    Patent number: 7127566
    Abstract: In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Siva Ramakrishnan, Ioannis Schoinas
  • Packet exchange for controlling system power modes
    Publication number: 20060080461
    Abstract: A method is described that, in order to change an operational state of a resource within a computing system that is shared by components of the computing system so that the computing system's power consumption is altered, sends a packet over one or more nodal hops within a packet based network within the computing system. The packet contains information pertaining to the power consumption alteration.
    Type: Application
    Filed: June 2, 2004
    Publication date: April 13, 2006
    Inventors: Jeffrey Wilcox, Shivnandan Kaushik, Stephen Gunther, Devadatta Bodas, Siva Ramakrishnan, Bernard Lint, Lance Hacking
  • Hardware coordination of power management activities
    Publication number: 20050273633
    Abstract: Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.
    Type: Application
    Filed: June 2, 2004
    Publication date: December 8, 2005
    Inventors: Jeffrey Wilcox, Shivnandan Kaushik, Stephen Gunther, Devadatta Bodas, Siva Ramakrishnan, David Poisner, Bernard Lint, Lance Hacking
  • Power state coordination between devices sharing power-managed resources
    Publication number: 20050273635
    Abstract: Methods and apparatuses for coordination of power state management in and electronic system.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 8, 2005
    Inventors: Jeffrey Wilcox, Shivnandan Kaushik, Stephen Gunther, Devadatta Bodas, Siva Ramakrishnan, David Poisner, Lance Hacking
  • Performing memory RAS operations over a point-to-point interconnect
    Publication number: 20050138304
    Abstract: In some embodiments, a memory transaction is received that was sent over an unordered interconnect. A determination is made as to whether an address conflict exists between the memory transaction and another memory transaction. If the address conflict exists the memory transaction is forwarded only after waiting until the conflict is resolved. Other embodiments are described and claimed.
    Type: Application
    Filed: December 18, 2003
    Publication date: June 23, 2005
    Inventors: Siva Ramakrishnan, Ioannis Schoinas
  • Synchronizing memory copy operations with memory accesses
    Publication number: 20050135176
    Abstract: In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.
    Type: Application
    Filed: December 18, 2003
    Publication date: June 23, 2005
    Inventors: Siva Ramakrishnan, Ioannis Schoinas
  • Method, system, and apparatus for memory compression with flexible in-memory cache
    Publication number: 20050114601
    Abstract: Method, systems and apparatus for a flexible compression architecture utilizing internal cache residing in main memory circuits.
    Type: Application
    Filed: November 26, 2003
    Publication date: May 26, 2005
    Inventor: Siva Ramakrishnan