Abstract: A multi-tone transceiver with a components forming a transmit path and a receive path configured to couple via a subscriber line to an opposing multi-tone transceiver for frequency division multiplexed multi-tone modulated communications therewith is disclosed. A noise margin channel identifier is configured to identify within a received tone set, discrete tones each associated with a corresponding one of at least two channels differing from one another in a relative noise margin of associated tones. A Viterbi decoder is responsive to the channel identification provided by the noise margin channel identifier to discretely decode each of the at least two channels; thereby improving the fidelity of the error correction provided by the Viterbi decoder by discretely processing the identified channels within the received set of tones.

Abstract: A computer system may comprise a receiver to perform equalization. The receiver comprises an equalizer. The equalizer may determine locations of a principal tap, a platform noise tap, and a pre-cursor tap in a feedforward path of an equalizer. Also, the equalizer may determine locations of a post-cursor tap, a cross-term tap, and a portable tap in a feedback path of the equalizer. The receiver may align the portable tap in the feedback path with the principal tap in the feedforward path. The platform noise tap may cancel the effect of platform noise on a principal located at the principal tap, thus enabling the computer system to operate effectively in severe platform noise environment. Also, the computer system may operate in statics and portable environment in which platform noise and AGWN may be present.

Abstract: A computer system may comprise a receiver to perform equalization. The receiver comprises an equalizer. The equalizer may determine locations of a principal tap, a platform noise tap, and a pre-cursor tap in a feedforward path of an equalizer. Also, the equalizer may determine locations of a post-cursor tap, a cross-term tap, and a portable tap in a feedback path of the equalizer. The receiver may align the portable tap in the feedback path with the principal tap in the feedforward path. The platform noise tap may cancel the effect of platform noise on a principal located at the principal tap, thus enabling the computer system to operate effectively in severe platform noise environment. Also, the computer system may operate in statics and portable environment in which platform noise and AGWN may be present.

Abstract: Method and apparatus for a filter micro-code accelerator are described.

Abstract: An apparatus includes a primary information storage unit, a secondary information storage unit, and an information processing unit. The primary information storage unit has a primary storage capacity. The secondary information storage unit has a secondary storage capacity. The secondary storage capacity is less than the primary storage capacity. The secondary information storage unit receives information from the primary information storage unit and the information processing unit processes the information to form a transform.

Abstract: An apparatus includes an instruction decoder, at least one control register coupled to the instruction decoder, and an add-compare-select (ACS) engine coupled to the at least one control register. The instruction decoder is operative to control the ACS engine to perform Viterbi decoding in response to the instruction decoder receiving a first instruction, and is operative to control the ACS engine to perform turbo decoding in response to the instruction decoder receiving a second instruction.

Abstract: A reconfigurable circuit includes a multiply-accumulator with a programmable pre-adder and also includes a scramble sequence generator. The scramble sequence generator may provide a despreading sequence to control inputs on the programmable pre-adder.

Abstract: An apparatus includes a primary information storage unit, a secondary information storage unit, and an information processing unit. The primary information storage unit has a primary storage capacity. The secondary information storage unit has a secondary storage capacity. The secondary storage capacity is less than the primary storage capacity. The secondary information storage unit receives information from the primary information storage unit and the information processing unit processes the information to form a transform.

Abstract: Method and apparatus for a filter micro-code accelerator are described.

Abstract: A programming tool parses and converts instructions for use in a reconfigurable processing element, such as a filter micro-coded accelerator.

Abstract: Method and apparatus for a trigger queue for a filter micro-code accelerator are described.

Abstract: An apparatus includes an instruction decoder, at least one control register coupled to the instruction decoder, and an add-compare-select (ACS) engine coupled to the at least one control register. The instruction decoder is operative to control the ACS engine to perform Viterbi decoding in response to the instruction decoder receiving a first instruction, and is operative to control the ACS engine to perform turbo decoding in response to the instruction decoder receiving a second instruction.