Patents by Inventor Siva Swaroop Vontela

Siva Swaroop Vontela has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for format efficient sector fragment processing
    Patent number: 9286915
    Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for format efficient processing of data fragments.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: March 15, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Scott M. Dziak, Siva Swaroop Vontela, Daniel A. Bressan
  • Detection of end of preamble in read channel without interpolation
    Patent number: 9111573
    Abstract: A method and system for detecting an end of a preamble without interpolation. The method includes receiving information from a zero phase start module, the information including a target phase constraint, a polyant, and a zero phase start phase. The method also includes selecting two samples per preamble cycle of short filter outputs and long filter outputs based on the target phase constraint, the polyant, and the zero phase start phase. The method further includes decimating the short filter outputs and the long filter outputs such that the selected two samples for each of the filters per preamble cycle are output upon decimation. The method additionally includes performing a sign comparison on the corresponding short filter and long filter outputs after decimation, wherein a sign mismatch of the corresponding short filter and long filter outputs indicates an end of a preamble.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: August 18, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Siva Swaroop Vontela, Scott M. Dziak
  • Double-step CORDIC processing for conventional signed arithmetic with decision postponing
    Patent number: 8775493
    Abstract: A double-step CORDIC algorithm is implemented for conventional signed arithmetic using multiple iteration stages in which at least one stage implements decision postponing, in which the decision for each stage is delayed until the next stage. In one implementation, the decision for the previous stage is implemented in parallel with the execution of CORDIC equation functions for the current stage. Implementing the double-step CORDIC with decision postponing algorithm can increase the speed of the CORDIC function compared to prior-art CORDIC implementations.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: July 8, 2014
    Assignee: LSI Corporation
    Inventors: Siva Swaroop Vontela, Vidya Prabhu, Priyabrata Kundu
  • Double-Step CORDIC Processing for Conventional Signed Arithmetic With Decision Postponing
    Publication number: 20120265796
    Abstract: A double-step CORDIC algorithm is implemented for conventional signed arithmetic using multiple iteration stages in which at least one stage implements decision postponing, in which the decision for each stage is delayed until the next stage. In one implementation, the decision for the previous stage is implemented in parallel with the execution of CORDIC equation functions for the current stage. Implementing the double-step CORDIC with decision postponing algorithm can increase the speed of the CORDIC function compared to prior-art CORDIC implementations.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Applicant: LSI CORPORATION
    Inventors: Siva Swaroop Vontela, Vidya Prabhu, Priyabrata Kundu