Abstract: Disclosed approaches for probing signals in a plurality of clock domains include inputting unsynchronized trigger signals from the plurality of clock domains to a plurality of instances of a multi-synchronizer circuit, respectively. Each instance of the multi-synchronizer circuit includes a plurality of synchronizer circuits. One or more of the plurality of synchronizer circuits synchronizes the respective unsynchronized trigger signal with one clock signal from the plurality of clock domains. Output of one of the one or more synchronizer circuits in each instance of the multi-synchronizer circuit is selected as a respective synchronized trigger signal. A trigger equation is evaluated based on a state of each respective synchronized trigger signal. A final trigger signal is generated based the evaluating of the trigger equation, a trigger marker is stored in a memory in response to a state of the final trigger signal, and states of probed signals are stored in the memory.

Abstract: Systems and methods gather data for debugging a circuit-under-test. The system includes a trigger-and-capture circuit, a data compressor, a direct memory access controller, and a memory controller. The trigger-and-capture circuit is coupled to the circuit-under-test for receiving signals from the circuit-under-test. The trigger-and-capture circuit is configured to assert a trigger signal when the signals match a trigger condition. The data compressor is configured to loss-lessly compress the signals into compressed data. The direct memory access controller is configured to generate write and read requests. The write requests write the compressed data to a memory integrated circuit die, and the read requests read the compressed data from the memory integrated circuit die. The memory controller is configured to perform the write and read requests.