Patents by Inventor Sivagnanam Parthasarathy

Sivagnanam Parthasarathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tiered error correction code (ECC) operations in memory
    Patent number: 11422885
    Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy
  • Partially written block treatment
    Patent number: 11416154
    Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
  • DESCRAMBLING OF SCRAMBLED LINEAR CODEWORDS USING NON-LINEAR SCRAMBLERS
    Publication number: 20220253224
    Abstract: A memory device configured to descramble scrambled composite data. In one approach, the scrambled composite data is provided by an XOR (exclusive OR operation) of more than one data set scrambled with non-linear scramblers. A memory device is configured to receive scramble codes generated by non-linear scramblers and perform an XOR of the scrambled composite data with the scramble codes to remove scrambling from the composite data. In one example, the scrambled data sets are data to be written to a NAND device at more than one bit per cell density (e.g., MLC, TLC, QLC, PLC, etc.). For example, the scrambled data sets may be written to the NAND device in more than one programming pass. In one example, the scrambled composite data is used to read the scrambled data sets that have been written in a first programming pass.
    Type: Application
    Filed: March 1, 2022
    Publication date: August 11, 2022
    Inventors: Patrick Robert Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak
  • BIT FLIPPING LOW-DENSITY PARITY-CHECK DECODERS WITH LOW ERROR FLOOR
    Publication number: 20220255561
    Abstract: A memory device having a Low-Density Parity-Check (LDPC) decoder that is energy efficient and has a low error floor. The decoder is configured to determine syndromes of bits in a codeword, select bits in the codeword based at least in part on the syndromes according to a first mode, and flip the selected bits in the codeword. The decoder can repeat the bit selection and flipping operations to iteratively improve the codeword and reduce parity violations. Further, the decoder can detect a pattern in parity violations of the codeword in its iterative bit flipping operations. In response, the decoder can change from the first mode to a second mode in bit selection for flipping. For example, the decoder can transmit from a dynamic syndrome mode to a static syndrome mode in response to the pattern of repeating a cycle of bit flipping iterations.
    Type: Application
    Filed: April 26, 2022
    Publication date: August 11, 2022
    Inventors: Mustafa N. Kaynak, Sivagnanam Parthasarathy
  • DATA RECOVERY USING A COMBINATION OF ERROR CORRECTION SCHEMES
    Publication number: 20220253354
    Abstract: Exemplary methods, apparatuses, and systems include receiving a request for a segment of data. The requested segment data is one of a plurality of segments of data in a stripe of data. A failure to decode the requested segment is detected. Each of the plurality of segments in the stripe other than the requested segment are read. Reading each segment includes reading raw encoded data and attempting to decode the raw encoded data, the result of reading each segment including decoded data when decoding is successful and the raw encoded data when decoding fails. A combined result of each read is generated. The combining includes combining decoded data for segments that were successfully decoded and the raw encoded data for segments for which decoding failed. A statistical model for the requested segment is updated using the combined result. The requested segment is decoded using the updated statistical model.
    Type: Application
    Filed: December 1, 2021
    Publication date: August 11, 2022
    Inventors: Dung V. Nguyen, Phong Sy Nguyen, Sivagnanam Parthasarathy
  • Voltage bin selection for blocks of a memory device after power up of the memory device
    Patent number: 11410734
    Abstract: A processing device of a memory sub-system is configured to detect a power on event associated with the memory device; scan one or more blocks of a plurality of blocks of the memory device to determine a corresponding time after program (TAP) associated with each block of the one or more blocks; estimate, based on the corresponding TAP of the each block of the one or more blocks, a duration of a power off state preceding the power on event; and update voltage bin assignments of the plurality of blocks associated with the memory device based on the duration of the power off state.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Sampath K Ratnam, Shane Nowell, Sivagnanam Parthasarathy, Mustafa N Kaynak, Karl D Schuh, Peter Feeley, Jiangang Wu
  • Self adapting iterative read calibration to retrieve data from memory cells
    Patent number: 11403042
    Abstract: A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: AbdelHakim S. Alhussien, Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat
  • Stopping criteria for layered iterative error correction
    Patent number: 11405058
    Abstract: The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mustafa N. Kaynak, William H. Radke, Patrick R. Khayat, Sivagnanam Parthasarathy
  • Managing defective bitline locations in a bit flipping decoder
    Patent number: 11398835
    Abstract: Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword has bits from defective bit locations and non-defective bit locations. A syndrome of a current copy of the codeword is determined. Channel information for non-defective bit locations is determined using the current copy of the codeword and the received codeword from the memory device. Energy function values are determined for bits of the codeword using the syndrome of the current copy. Determining the energy function values includes using the channel information for bits in non-defective bit locations and omitting channel information for bits in defective bit locations. One or more bits of the codeword are flipped in response to the energy function values for the one or more bits satisfying a bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: July 26, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Mustafa N. Kaynak, Sivagnanam Parthasarathy
  • GROUPING BLOCKS BASED ON POWER CYCLE AND POWER ON TIME
    Publication number: 20220229554
    Abstract: A block family associated with a memory device is initialized. An initial value of a power cycle count associated with the memory device is stored. Responsive to programming a block residing in the memory device, the block is associated with the block family. Responsive to determining that a current value of the power cycle count exceeds the initial value of the power cycle count, the block family is closed. Responsive to determining that a time period that has elapsed since initializing the block family exceeds a threshold period, the block family is closed.
    Type: Application
    Filed: January 20, 2021
    Publication date: July 21, 2022
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Peter Feeley, Karl D. Schuh
  • Mitigating a voltage condition of a memory cell in a memory sub-system
    Patent number: 11393541
    Abstract: A determination that a programming operation has been performed on a memory cell can be made. An amount of time that has elapsed since the programming operation has been performed on the memory cell can be identified. A determination as to whether the amount of time that has elapsed satisfies a threshold time condition can be made. In response to determining that the amount of time that has elapsed satisfies the threshold time condition an operation can be performed on the memory cell to change or maintain a voltage condition of the memory cell.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
  • Error correction based on rate adaptive low density parity check (LDPC) codes with flexible column weights in the parity check matrices
    Patent number: 11394403
    Abstract: Methods and system for error correction based on rate adaptive LDPC codes with flexible column weights in the parity check matrices are described. Data is encoded according to a first encoding parity check matrix of a first Low Density Parity Check (LDPC) code to obtain a first codeword with first parities. The first codeword is encoded according to a second encoding parity check matrix of a second LDPC code to obtain second parities. The first codeword is received. Responsive to failure of error correction of the first codeword based on the first parities, the second parities are received. The first codeword is corrected based on the second parities and a decoding parity check matrix of a rate adaptive LDPC code that is constructed by vertically concatenating the second encoding parity check matrix and the first encoding parity check matrix and adding an all-zero sub-matrix to complete its dimensions.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: July 19, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Eyal En Gad, Sivagnanam Parthasarathy, Zhengang Chen, Mustafa N. Kaynak, Yoav Weinberg
  • Iterative error correction with adjustable parameters after a threshold number of iterations
    Patent number: 11374592
    Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 28, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Eyal En Gad, Zhengang Chen, Sivagnanam Parthasarathy, Yoav Weinberg
  • Proactive read disturb mitigation
    Patent number: 11361831
    Abstract: A request is received to perform a set of read operations using a memory device. The set of read operations are divided into a plurality of subsets of read operations. A first read operation is selected from a first subset of read operations of the plurality of subsets of read operations. The first read operation is performed on a first location on a memory device. One or more first data integrity scan operations is performed on one or more second locations on the memory device adjacent to the first location to determine one or more first reliability statistics associated with the one or more second locations.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Saeed Sharifi Tehrani, Sivagnanam Parthasarathy
  • IDENTIFICATION AND CACHING OF FREQUENT READ DISTURB AGGRESSORS
    Publication number: 20220179795
    Abstract: Exemplary methods, apparatuses, and systems include receiving a read operation directed to an aggressor location. An integrity scan of a victim location of the aggressor location is performed to determine an error value for the victim location. Data from the aggressor location is copied to a cache in response to determining the error value for the victim location satisfies a first error value threshold. The cache is a different type of memory from the aggressor location.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 9, 2022
    Inventors: Saeed Sharifi Tehrani, Sivagnanam Parthasarathy, Aniryudh Reddy Durgam
  • Determine optimized read voltage via identification of distribution shape of signal and noise characteristics
    Patent number: 11355203
    Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: AbdelHakim S. Alhussien, James Fitzpatrick, Patrick Robert Khayat, Sivagnanam Parthasarathy
  • Coarse Calibration based on Signal and Noise Characteristics of Memory Cells Collected in Prior Calibration Operations
    Publication number: 20220172787
    Abstract: A memory device to perform a calibration of read voltages of a group of memory cells. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine an amount of accumulated storage charge loss in the group of memory cells. Subsequently, the memory device can perform a read voltage calibration based on the determined amount of accumulated storage charge loss and a look up table.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Inventors: Patrick Robert Khayat, James Fitzpatrick, AbdelHakim S. Alhussien, Sivagnanam Parthasarathy
  • Bit flipping low-density parity-check decoders with low error floor
    Patent number: 11349498
    Abstract: A memory device having a Low-Density Parity-Check (LDPC) decoder that is energy efficient and has a low error floor. The decoder is configured to determine syndromes of bits in a codeword, select bits in the codeword based at least in part on the syndromes according to a first mode, and flip the selected bits in the codeword. The decoder can repeat the bit selection and flipping operations to iteratively improve the codeword and reduce parity violations. Further, the decoder can detect a pattern in parity violations of the codeword in its iterative bit flipping operations. In response, the decoder can change from the first mode to a second mode in bit selection for flipping. For example, the decoder can transmit from a dynamic syndrome mode to a static syndrome mode in response to the pattern of repeating a cycle of bit flipping iterations.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mustafa N. Kaynak, Sivagnanam Parthasarathy
  • Estimating an error rate associated with memory
    Patent number: 11334413
    Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
  • Improved Reading of Soft Bits and Hard Bits from Memory Cells
    Publication number: 20220139468
    Abstract: A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien