Abstract: The disclosure relates to sharing real-time multimedia content. The method may include identifying an application for sharing by a first device, discovering one or more second devices by the first device, independent of a technology or a platform of the devices, applying communication protocols and creating an association between the first device and the one or more second devices, and determining multimedia capabilities of the one or more second devices. Furthermore, such an example method may include selecting at least a portion of the screen of a first device for sharing based at least on the determined multimedia capabilities of the second devices, computing application associated performance parameters based at least on a type of content and transmitting the selected portion of the screen of the first device to the one or more second devices over the wireless connection.

Abstract: The disclosure relates to sharing real-time multimedia content. The method may include identifying an application for sharing by a first device, discovering one or more second devices by the first device, independent of a technology or a platform of the devices, applying communication protocols and creating an association between the first device and the one or more second devices, and determining multimedia capabilities of the one or more second devices. Furthermore, such an example method may include selecting at least a portion of the screen of a first device for sharing based at least on the determined multimedia capabilities of the second devices, computing application associated performance parameters based at least on a type of content and transmitting the selected portion of the screen of the first device to the one or more second devices over the wireless connection.

Abstract: A pseudo CAM (PCAM) can be implemented using SRAM to minimize latency associated with a traditional CAM. On receiving a key at a memory controller that executes operations on the PCAM, a hash value of the received key can be calculated. Based on the hash value of the received key, one of a plurality of memory sub-trees comprising a subset of memory locations, that is associated with the received key can be identified. A binary search can be executed on the subset of memory locations that constitute the identified memory sub-tree to identify a memory location at which a data entry comprising the received key is stored. The data entry comprising the received key and corresponding content can then either be retrieved or deleted. Alternatively, a binary search can be executed to identify the memory location where a new data entry comprising the received key should be stored.

Abstract: An on-chip testing unit can be implemented in an integrated circuit (e.g., a SoC) to validate the operation of cache memories associated with a processor of the integrated circuit. For each testing instruction to be executed by the processor for testing a cache memory, the testing unit can intercept information (e.g., address, data, and/or control signals) generated by the processor in response to executing the instruction. The testing unit can determine whether information generated by the processor matches corresponding expected information associated with the instruction. This can enable the testing unit to determine whether the processor can correctly identify an address from which the next instruction is to be fetched, can ensure consistency between data in the cache memories and persistent storage devices, and whether the processor is operating as expected. An error notification can be generated if the information generated by the processor does not match the expected information.