Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller’s performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Abstract: A circuit provides for processing and routing peer-to-peer (P2P) traffic. A bus request queue store a data request received from a first peer device. A decoder compares an address portion of the data request against an address map to determine whether the data request is directed to either a second peer device or a local memory. A bus interface unit, in response to the data request being directed to the second peer device, 1) generates a memory access request from the bus request and 2) transmits the memory access request toward the second peer device via a bus. A memory controller, in response to the data request being directed to a local memory, accesses the local memory to perform a memory access operation based on the data request.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Abstract: Method and apparatus for communicating information regarding distributed generator (DG) systems.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Abstract: An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.

Abstract: Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.

Abstract: Devices, systems, and methods for implementing a scalable extended basic input/output system (BIOS) region that increases the BIOS footprint of a system, are provided and described. In addition to a traditional BIOS region located in the memory mapped input/output (MMIO) low region, an extended BIOS region is initialized in a MMIO area of the system address map, where both regions are accessed by MMIO access requests.

Abstract: Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.

Abstract: An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.

Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.

Abstract: Devices, systems, and methods for implementing a scalable extended basic input/output system (BIOS) region that increases the BIOS footprint of a system, are provided and described. In addition to a traditional BIOS region located in the memory mapped input/output (MMIO) low region, an extended BIOS region is initialized in a MMIO area of the system address map, where both regions are accessed by MMIO access requests.

Abstract: Technology for a computing system is described. The computing system can include memory, a controller, and a security management module. The controller can receive a block erase command for erasing data stored in a block of memory. The controller can store information associated with the block erase command in a store, wherein the information includes a block address associated with the data to be erased based on the block erase command. The security management module can read block addresses from the store, update a block erase count array over a defined interval to include block addresses read from the store, compare the block erase count array to a defined threshold, identify block addresses for which the block erase count array is above the defined threshold, and deny subsequent block erase commands for the identified block addresses.

Abstract: Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality of exclusive OR logic include first exclusive OR logic and second exclusive OR logic. First Galois Field multiplier logic multiplies a first output from the first exclusive OR logic and a first portion of a plurality of portions of the input data. Second Galois Field multiplier logic multiplies a second output from the second exclusive OR logic and a second portion of the plurality of portions of the input data. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.

Abstract: Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality of exclusive OR logic include first exclusive OR logic and second exclusive OR logic. First Galois Field multiplier logic multiplies a first output from the first exclusive OR logic and a first portion of a plurality of portions of the input data. Second Galois Field multiplier logic multiplies a second output from the second exclusive OR logic and a second portion of the plurality of portions of the input data. Other embodiments are also disclosed and claimed.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.