Patents by Inventor Sivakumar Ramakrishnan

Sivakumar Ramakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for deep sub-micron design of integrated circuits
    Patent number: 7694257
    Abstract: A technique for adding filler metal polygons in metal layers on a chip area of an IC design. In one example embodiment, this is accomplished by computing a size of a filler metal polygon using chip design layout data. One or more regions on the metal layers of the IC design that do not meet metal density requirements are then identified. The identified one or more regions are then filled with one or more filler metal polygons as a function of the metal density requirement and coupling capacitance between metal lines.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: April 6, 2010
    Assignee: Analog Devices, Inc.
    Inventors: Sivakumar Ramakrishnan, Narasimha Murthy Padmanabhan
  • Method and apparatus for deep sub-micron design of integrated circuits
    Publication number: 20060035456
    Abstract: A technique for adding filler metal polygons in metal layers on a chip area of an IC design. In one example embodiment, this is accomplished by computing a size of a filler metal polygon using chip design layout data. One or more regions on the metal layers of the IC design that do not meet metal density requirements are then identified. The identified one or more regions are then filled with one or more filler metal polygons as a function of the metal density requirement and coupling capacitance between metal lines.
    Type: Application
    Filed: June 15, 2005
    Publication date: February 16, 2006
    Inventors: Sivakumar Ramakrishnan, Narasimha Padmanabhan