Patents by Inventor Sivalingam Sivananthan

Sivalingam Sivananthan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100096001
    Abstract: A Group II-VI photovoltaic solar cell comprising at least two and as many as five subcells stacked upon one another. Each subcell has an emitter layer and a base layer, with the base of the first subcell being made of silicon, germanium, or silicon-germanium. The remaining subcells are stacked on top of the first subcell and are ordered such that the band gap gets progressively smaller with each successive subcell. Moreover, the thicknesses of each subcell are optimized so that the current from each subcell is substantially equal to the other subcells in the stack. Examples of suitable Group II-VI semiconductors include CdTe, CdSe, CdSeTe, CdZnTe, CdMgTe, and CdHgTe.
    Type: Application
    Filed: October 30, 2008
    Publication date: April 22, 2010
    Applicant: EPIR TECHNOLOGIES, INC.
    Inventors: Sivalingam SIVANANTHAN, Wayne H. LAU, Christoph GREIN, James W. GARLAND
  • Publication number: 20090321642
    Abstract: A detector of incident infrared radiation has a first region with a first spectral response, and a second region with a second, different spectral response. The second absorption region is stacked on the first and may be separated therefrom by a region in which the chemical composition of the compound semiconductor is graded. Separate contacts are provided to the first and second absorption regions and a further common contact is provided so as to permit the application of either a bias voltage or a skimming voltage across the respective pn junctions. The detector may be operated such that a preselected one of the absorption regions responds to incident infrared radiation of a predetermined waveband while the other absorption region acts as a skimmer of dark current, thereby enhancing the signal to noise ratio of the detector.
    Type: Application
    Filed: April 30, 2008
    Publication date: December 31, 2009
    Applicant: EPIR TECHNOLOGIES, INC.
    Inventors: Silviu VELICU, Christoph GREIN, Sir B. Rafol, Sivalingam SIVANANTHAN
  • Publication number: 20090261442
    Abstract: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. An extraction region is disposed on a first side of the active region and extracts minority carriers from the active region. It also has majority carriers within the extraction region flowing toward the active region in a condition of reverse bias. An exclusion region is disposed on a second side of the active region and has minority carriers within the exclusion region flowing toward the active region. It receives majority carriers from the active region. At least one of the extraction and exclusion region provides a barrier for substantially reducing flow of one of the majority carriers or the minority carriers, whichever is flowing toward the active region, while permitting flow of the other minority carriers or majority carriers flowing out of the active region.
    Type: Application
    Filed: April 17, 2008
    Publication date: October 22, 2009
    Applicant: EPIR TECHNOLOGIES, INC.
    Inventors: Christoph H. Grein, Silviu Velicu, Sivalingam Sivananthan
  • Patent number: 7045378
    Abstract: A photosensitive diode has superlattice exclusion region formed from a stack of first and second layers. The first layers are penetrated by minority carriers using quantum mechanical tunneling and reduce minority carrier mobility. The second layers have a sufficiently low bandgap that the tunneling minority carriers can reach an active region of the diode. The process of successively forming first and second layers is repeated until the exclusion region is at least three times the minority carrier diffusion length.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: May 16, 2006
    Assignee: EPIR Technologies, Inc.
    Inventors: Christoph H. Grein, Silviu Velicu, Sivalingam Sivananthan
  • Patent number: 6906358
    Abstract: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. At least one extraction region is disposed on a first side of the active region and has a majority carrier of the second conductivity type. Carriers of the second conductivity type are extracted from the active region and into the extraction region under a condition of reverse bias. At least one exclusion region is disposed on a second side of the active region and has a majority carrier of the first conductivity type. The exclusion region prevents entry of its minority carriers, which are of the second conductivity type, into the active region while in a condition of reverse bias. The exclusion region includes a superlattice with a plurality of layers.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: June 14, 2005
    Assignee: EPIR Technologies, Inc.
    Inventors: Christoph H. Grein, Silviu Velicu, Sivalingam Sivananthan
  • Publication number: 20050040428
    Abstract: A photosensitive diode has superlattice exclusion region formed from a stack of first and second layers. The first layers are penetrated by minority carriers using quantum mechanical tunneling and reduce minority carrier mobility. The second layers have a sufficiently low bandgap that the tunneling minority carriers can reach an active region of the diode. The process of successively forming first and second layers is repeated until the exclusion region is at least three times the minority carrier diffusion length.
    Type: Application
    Filed: September 24, 2004
    Publication date: February 24, 2005
    Inventors: Christoph Grein, Silviu Velicu, Sivalingam Sivananthan
  • Publication number: 20040150002
    Abstract: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. At least one extraction region is disposed on a first side of the active region and has a majority carrier of the second conductivity type. Carriers of the second conductivity type are extracted from the active region and into the extraction region under a condition of reverse bias. At least one exclusion region is disposed on a second side of the active region and has a majority carrier of the first conductivity type. The exclusion region prevents entry of its minority carriers, which are of the second conductivity type, into the active region while in a condition of reverse bias. The exclusion region includes a superlattice with a plurality of layers.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 5, 2004
    Applicant: SMART PIXEL, INC.
    Inventors: Christoph H. Grein, Silviu Velicu, Sivalingam Sivananthan
  • Patent number: 6657194
    Abstract: At a face of a silicon semiconductor substrate tilted about one degree from a [100] orientation, a readout integrated circuit (ROIC) is implemented, specially designed and fabricated for direct epitaxial growth. Layers of II-VI semiconductor material, preferably including layers of HgCdTe of different bandgaps, are successively and monolithically grown on the face by molecular beam epitaxy (MBE) within a window masking the face and then patterned and wet-etched to create mesas of two-color detector elements in an array. Preferably a beginning buffer layer of CdTe is grown to minimize crystalline mismatch between the Si and the HgCdTe. Sloped sidewalls of the mesas ensure good step coverage of the conductive interconnects from the detector elements to the ROIC.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: December 2, 2003
    Assignee: EPIR Technologies, Inc.
    Inventors: Renganathan Ashokan, Paul Boieriu, Yuanping Chen, Jean-Pierre Faurie, Sivalingam Sivananthan
  • Publication number: 20030160172
    Abstract: Multispectral infrared detectors are needed for advanced imaging systems with capabilities to discriminate actual targets against decoys. Simultaneous detection of the infrared radiation emitted by the target in more than one wavelength range has significant advantages for this purpose. In the current invention, a technology for producing a plurality of multi-color infrared sensing elements in a monolithic array format is provided. Each element has a multi-layer structure of mercury cadmium telluride (HgCdTe), a group II-VI semiconductor. The unit cell of the integrated detector consists of two co-located detectors, each sensitive to a different infrared wavelength. The prior art to produce such infrared device arrays is ‘hybrid technology’, meaning the infrared sensing elements and the read-out electronics are fabricated on two different materials-silicon and HgCdTe and joined together by indium pillars/bumps.
    Type: Application
    Filed: April 13, 2001
    Publication date: August 28, 2003
    Applicant: EPIR LTD.
    Inventors: Renganathan Ashokan, Paul Boieriu, Yuanping Chen, Jean-Pierre Faurie, Sivalingam Sivananthan
  • Publication number: 20030102432
    Abstract: An infrared sensing device including a multi-layer II-VI semiconductor material grown by molecular beam epitaxy on a readout circuit fabricated on silicon substrate having a orientation one degree tilted from the (100) direction is provided in this invention. A method to grow single crystalline mercury cadmium telluride multi-layer structure on custom-designed readout circuit (ROIC) is provided. Due to the height difference of more than 15 micron between the two planes containing the detector output gates and the ROIC signal input gates, a mesa with at least one sloped side is fabricated and the interconnecting metal electrodes running on them to connect the detector output to ROIC input. Planar photovoltaic junctions are fabricated selectively on the II-VI mesa structure formed on ROIC. At least one infrared detecting cell being formed in the mesa, with a conductor interconnect layer connecting the detection cell to the readout integrated circuit.
    Type: Application
    Filed: April 12, 2001
    Publication date: June 5, 2003
    Applicant: EPIR LTD.
    Inventors: Paul Boieriu, Renganathan Ashokan, Yuanping Chen, Jean-Pierre Faurie, Sivalingam Sivananthan