Patents by Inventor Sivananda K. Kanakasabapathy
Sivananda K. Kanakasabapathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096627Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.Type: ApplicationFiled: April 27, 2023Publication date: March 21, 2024Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Patent number: 11894462Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.Type: GrantFiled: October 26, 2021Date of Patent: February 6, 2024Assignee: Adeia Semiconductor Solutions LLCInventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu
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Patent number: 11670510Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.Type: GrantFiled: May 24, 2021Date of Patent: June 6, 2023Assignee: Tessera LLCInventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Patent number: 11646221Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.Type: GrantFiled: November 25, 2019Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Sean D. Burns, Lawrence A. Clevenger, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Nicole Saulnier
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Patent number: 11315922Abstract: The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.Type: GrantFiled: March 3, 2020Date of Patent: April 26, 2022Assignee: International Business Machines CorporationInventors: Andrew M. Greene, Balasubramanian Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre
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Patent number: 11276767Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.Type: GrantFiled: March 15, 2017Date of Patent: March 15, 2022Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P. V. Seshadri, Rajasekhar Venigalla
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Publication number: 20220069118Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.Type: ApplicationFiled: October 26, 2021Publication date: March 3, 2022Inventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu
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Patent number: 11227793Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.Type: GrantFiled: May 1, 2018Date of Patent: January 18, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sean D. Burns, Lawrence A. Clevenger, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Nicole Saulnier
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Patent number: 11189729Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.Type: GrantFiled: November 15, 2019Date of Patent: November 30, 2021Assignee: Tessera, Inc.Inventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu
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Patent number: 11152489Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.Type: GrantFiled: November 12, 2019Date of Patent: October 19, 2021Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P. V. Seshadri, Rajasekhar Venigalla
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Patent number: 11145658Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.Type: GrantFiled: October 21, 2019Date of Patent: October 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang
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Publication number: 20210280422Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Patent number: 11107821Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.Type: GrantFiled: May 15, 2019Date of Patent: August 31, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodoras E. Standaert, Xinhui Wang
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Patent number: 11094824Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, and a bottom substrate portion formed from a same material as an underlying substrate. An isolation dielectric layer is formed between and around the bottom substrate portion of the one or more fins. A single oxide layer is formed in direct contact with the bottom substrate portion of each fin, between the bottom substrate portion of each fin and the isolation dielectric layer. A gate dielectric is formed over the one or more fins and between a straight sidewall of at least a top portion of the single oxide layer and an adjacent sidewall of the one or more fins, in contact with both the straight sidewall and the bottom substrate portion.Type: GrantFiled: November 15, 2019Date of Patent: August 17, 2021Assignee: Tessera, Inc.Inventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K Kanakasabapathy, Peng Xu
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Patent number: 11081566Abstract: Semiconductor devices and methods of forming the same include forming a gate stack in contact with sidewalls of a semiconductor fin and on a bottom spacer over a bottom source/drain region. An encapsulating material is selectively deposited over the gate stack, leaving the bottom spacer exposed. An inter-layer dielectric is formed over the encapsulating material. A via is formed in the inter-layer dielectric to contact the bottom source/drain layer.Type: GrantFiled: March 15, 2019Date of Patent: August 3, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Su Chen Fan, Ekmini A. De Silva, Sivananda K. Kanakasabapathy
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Patent number: 11075281Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.Type: GrantFiled: November 12, 2019Date of Patent: July 27, 2021Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P. V. Seshadri, Rajasekhar Venigalla
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Patent number: 11056493Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.Type: GrantFiled: March 7, 2019Date of Patent: July 6, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang
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Patent number: 11018007Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.Type: GrantFiled: November 6, 2019Date of Patent: May 25, 2021Assignee: Tessera, Inc.Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Patent number: 10957583Abstract: An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a ? line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a ? line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an ? line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a ??? jog; a ??? jog; an ??? jog; a ??? jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.Type: GrantFiled: August 28, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Patent number: 10957694Abstract: A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.Type: GrantFiled: January 24, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karthik Balakrishnan, Keith E. Fogel, Sivananda K. Kanakasabapathy, Alexander Reznicek