Abstract: In one embodiment, a method for performing an analysis of a synthesized clock tree can include: displaying a plurality of variation parameters and one or more analysis values on a display screen; accepting a first signal from a user input device to select one of the variation parameters; accepting a second signal from a user input device to select one or more of the analysis values; and displaying a plurality of pins from the synthesized clock tree with the selected variation parameter and the selected one or more analysis values on the display screen.

Abstract: In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design. The clock tree nodes may be arranged to distribute the clock signal to the sink pins. In synthesizing the clock tree, the sink pins may be clustered into one or more clusters. Clock tree nodes may be placed for the clock tree to distribute the clock signal to the one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters. For example, the clock tree timing variation parameters includes timing information for multiple process corners and/or multiple modes of operation.

Abstract: In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design. The clock tree nodes may be arranged to distribute the clock signal to the sink pins. In synthesizing the clock tree, the sink pins may be clustered into one or more clusters. Clock tree nodes may be placed for the clock tree to distribute the clock signal to the one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters. For example, the clock tree timing variation parameters includes timing information for multiple process corners and/or multiple modes of operation.

Abstract: In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design. The clock tree nodes may be arranged to distribute the clock signal to the sink pins. In synthesizing the clock tree, the sink pins may be clustered into one or more clusters. Clock tree nodes may be placed for the clock tree to distribute the clock signal to the one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters. For example, the clock tree timing variation parameters includes timing information for multiple process corners and/or multiple modes of operation.

Abstract: A method for building a clock tree for an integrated circuit design. The clock tree has a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design to distribute the clock signal to the sink pins, which are clustered into one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters.

Abstract: In one embodiment, a method for performing an analysis of a synthesized clock tree can include: displaying a plurality of variation parameters and one or more analysis values on a display screen; accepting a first signal from a user input device to select one of the variation parameters; accepting a second signal from a user input device to select one or more of the analysis values; and displaying a plurality of pins from the synthesized clock tree with the selected variation parameter and the selected one or more analysis values on the display screen.

Abstract: A method for building a clock tree for an integrated circuit design. The clock tree has a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design to distribute the clock signal to the sink pins, which are clustered into one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters.

Abstract: In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design. The clock tree nodes may be arranged to distribute the clock signal to the sink pins. In synthesizing the clock tree, the sink pins may be clustered into one or more clusters. Clock tree nodes may be placed for the clock tree to distribute the clock signal to the one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters. For example, the clock tree timing variation parameters includes timing information for multiple process corners and/or multiple modes of operation.

Abstract: In one embodiment, a method for performing an analysis of a synthesized clock tree can include: displaying a plurality of variation parameters and one or more analysis values on a display screen; accepting a first signal from a user input device to select one of the variation parameters; accepting a second signal from a user input device to select one or more of the analysis values; and displaying a plurality of pins from the synthesized clock tree with the selected variation parameter and the selected one or more analysis values on the display screen.