Abstract: The present invention provides a physical layer and associated signal processing method for clock domain transfer of quarter-rate data. In the embodiments of the present invention, the quarter-rate data is processed by many sampling circuits by using a first clock signal, a second clock signal and a third clock signal, and phases of these clock signals are aligned by using a training mechanism to that the clock signals have better timing margins.

Abstract: A level shifter and an electronic device are provided. The electronic device includes a digital circuit and a level shifter. The level shifter converts a first and a second input signals to an output signal. The level shifter includes a cross-coupled circuit, a protection circuit, and a pull-down module. The cross-coupled circuit includes a first and a second pull-up transistors. The protection circuit includes a first and a second protection transistors. The pull-down module includes a first and a second pull-down circuits and a first and a second switching circuits. The first and the second pull-up transistors, the first and the second protection transistors, and the first and the second pull-down circuits are selectively switched on in response to the first and the second input signals. The digital circuit receives the output signal from the level shifter.

Abstract: The present invention provides a physical layer and associated signal processing method for clock domain transfer of quarter-rate data.

Abstract: Disclosed is an approach for performing auto-classification of documents. A machine learning framework is provided to analyze the document, where labels associated with certain documents can be propagated to other documents.

Abstract: As a default, a global permissions model is established. The global permissions model serves for applying a first set of resource access permissions to shared content objects. Additionally, a set of context-aware access policies that govern user interactions over the shared content object is established. When a particular user requests an interaction over a shared content object, then interaction attributes associated with the request are gathered. The context-aware access policies are applied to the request by determining a set of extensible access permissions that are derived from the interaction attributes. The context-aware access policies are enforced by overriding the first set of resource access permissions with dynamically-determined access permissions. When a particular access request is denied, a response is generated in accordance with the set of extensible access permissions and the user is notified. In some cases, the access request is permitted, but only after the user provides a justification.

Abstract: Disclosed is an approach for performing auto-classification of documents. A machine learning framework is provided to analyze the document, where labels associated with certain documents can be propagated to other documents.

Abstract: A gate signal control circuit of a DDR memory system includes a comparing circuit, a flag generator and a signal generator. The comparing circuit receives a first data strobe signal and a second data strobe signal, and generates an internal data strobe signal. The flag generator receives a physical layer clock signal and a read enable signal, and generates plural flag signals. The signal generator receives the internal data strobe signal and the plural flag signal, and generates a gate signal. When plural read commands are issued, the flag generator sets the flag signals according to the physical layer clock signal and the read enable signal. When a read data is received, the signal generator opens the gate signal according to a preamble, and the signal generator samples the plural flag signals to determine the timing of closing the gate signal.

Abstract: A gate signal control circuit of a DDR memory system includes a comparing circuit, a flag generator and a signal generator. The comparing circuit receives a first data strobe signal and a second data strobe signal, and generates an internal data strobe signal. The flag generator receives a physical layer clock signal and a read enable signal, and generates plural flag signals. The signal generator receives the internal data strobe signal and the plural flag signal, and generates a gate signal. When plural read commands are issued, the flag generator sets the flag signals according to the physical layer clock signal and the read enable signal. When a read data is received, the signal generator opens the gate signal according to a preamble, and the signal generator samples the plural flag signals to determine the timing of closing the gate signal.

Abstract: A method for controlling a multi-cycle write leveling process in a memory system is provided. After a write leveling process is completed and before a write training process is performed, the multi-cycle write leveling process is performed. Consequently, when a DDR memory of the memory system receives a clock signal and a first data strobe signal, the DDR memory can confirm that the signal edges of the clock signal and the first data strobe signal are aligned with each other and the signal edges are accurate.

Abstract: A method for performing duty-cycle correction of an output clock in a Double Data Rate (DDR) system includes: setting a fixed delay of a rising-edge of the output clock as a parameter X which is equal to a digital Master Delay Locked Loop (MDLL) code of the DDR system multiplied by a percentage representing an estimated distortion of the duty-cycle of the output clock from a desired duty-cycle; shifting the rising-edge of the output clock by the fixed delay; and determining whether a duty cycle of the shifted output clock meets the desired duty-cycle. When a duty-cycle of the shifted output clock meets the desired duty-cycle, the fixed rising-edge delay is taken as a final delay code for the output clock; otherwise, a falling-edge of the output clock is shifted by an amount in a range between 0 and NX, wherein N is an integer.

Abstract: As a default, a global permissions model is established. The global permissions model serves for applying a first set of resource access permissions to shared content objects. Additionally, a set of context-aware access policies that govern user interactions over the shared content object is established. When a particular user requests an interaction over a shared content object, then interaction attributes associated with the request are gathered. The context-aware access policies are applied to the request by determining a set of extensible access permissions that are derived from the interaction attributes. The context-aware access policies are enforced by overriding the first set of resource access permissions with dynamically-determined access permissions. When a particular access request is denied, a response is generated in accordance with the set of extensible access permissions and the user is notified. In some cases, the access request is permitted, but only after the user provides a justification.

Abstract: As a default, a global permissions model is established. The global permissions model serves for applying a first set of resource access permissions to shared content objects. Additionally, a set of context-aware access policies that govern user interactions over the shared content object is established. When a particular user requests an interaction over a shared content object, then interaction attributes associated with the request are gathered. The context-aware access policies are applied to the request by determining a set of extensible access permissions that are derived from the interaction attributes. The context-aware access policies are enforced by overriding the first set of resource access permissions with dynamically-determined access permissions. When a particular access request is denied, a response is generated in accordance with the set of extensible access permissions and the user is notified. In some cases, the access request is permitted, but only after the user provides a justification.

Abstract: Disclosed is an approach for performing auto-classification of documents. A machine learning framework is provided to analyze the document, where labels associated with certain documents can be propagated to other documents.

Abstract: A calibratable delay chain having a delay chain and an adjustment circuitry varying a delay of each of the plurality of delay stages in the chain. The calibration circuitry is configured to calibrate a delay of the delay chain. The calibration circuitry includes calibration control circuitry for controlling the calibration and supplying the input value to an adjustment circuitry. Output selection circuitry is provided to select an output from a predetermined point along the delay chain. A bypass path bypasses the delay chain and a digital comparator compares an output from the delay chain and an output from the bypass path. An analogue comparator compares an output from the delay chain and an output from the bypass path. The calibration control circuitry is configured to control the output selection circuitry to output a signal from one point on the delay chain to the digital comparator.

Abstract: A calibratable delay chain having a delay chain and an adjustment circuitry varying a delay of each of the plurality of delay stages in the chain. The calibration circuitry is configured to calibrate a delay of the delay chain. The calibration circuitry includes calibration control circuitry for controlling the calibration and supplying the input value to an adjustment circuitry. Output selection circuitry is provided to select an output from a predetermined point along the delay chain. A bypass path bypasses the delay chain and a digital comparator compares an output from the delay chain and an output from the bypass path. An analogue comparator compares an output from the delay chain and an output from the bypass path. The calibration control circuitry is configured to control the output selection circuitry to output a signal from one point on the delay chain to the digital comparator.

Abstract: Calibration circuitry 42 for an off-chip driver circuit 4 and/or an on-die termination circuit 8 is provided using a parallel network of main transistors controlled by a N-bit calibration value. During the calibration operation, the N-bit calibration value is varied until a threshold impedance value is crossed by the combination of the main transistors. A rounding transistor 52 is then used to determine which of the N-bit calibration values produces a combined impedance closest to the designed threshold impedance.

Abstract: A processor-implemented means of designing a power pad layout includes determining a location of at least one ESD structure so as to minimize a placement cost and determining a location of at least one connection between the at least one ESD structure and at least one power ring. The step of determining a location of at least one connection between the ESD structure and at least one power ring may include the steps of determining a minimum spanning tree of elements associated with a given power ring; and back-tracing through a minimum spanning tree of elements associated with a given power ring in order to determine a minimal list of routed paths among the elements.

Abstract: A processor-implemented means of designing a power pad layout includes determining a location of at least one ESD structure so as to minimize a placement cost and determining a location of at least one connection between the at least one ESD structure and at least one power ring. The step of determining a location of at least one connection between the ESD structure and at least one power ring may include the steps of determining a minimum spanning tree of elements associated with a given power ring; and back-tracing through a minimum spanning tree of elements associated with a given power ring in order to determine a minimal list of routed paths among the elements.