Patents by Inventor Sivayya Ayinala

Sivayya Ayinala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7761617
    Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: July 20, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Franck Seigneret, Sivayya Ayinala, Nabil Khalifa, Praveen Kolli, Prabha Atluri
  • Patent number: 7373437
    Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes a data FIFO (210) which is shared by all of the logical channels and the FIFO depth can be allocated dynamically allowing for the maximum number of channels to be scheduled and concurrently active. The FIFO (210) can also be allocated to a single channel if there is only one logical channel active. The FIFO (210) increases the DMA's transfer performance, pre-fetch capacity and buffering, while maximizing pipelining.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: May 13, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Franck Seigneret, Nabil Khalifa, Sivayya Ayinala, Praveen Kolli
  • Publication number: 20060179172
    Abstract: A method and system for reducing the power consumption of a direct memory access (DMA) controller. A preferred method, for example, comprises: queuing a first DMA request in a queue; responding to the first queued DMA request when the computer system resources necessary for a DMA transfer are available; and placing at least some components of the computer system into a reduced power consumption state when the computer system resources necessary for the DMA transfer are not available.
    Type: Application
    Filed: January 28, 2005
    Publication date: August 10, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Sivayya Ayinala, Praveen Kolli
  • Publication number: 20060080477
    Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes a data FIFO (210) which is shared by all of the logical channels and the FIFO depth can be allocated dynamically allowing for the maximum number of channels to be scheduled and concurrently active. The FIFO (210) can also be allocated to a single channel if there is only one logical channel active. The FIFO (210) increases the DMA's transfer performance, pre-fetch capacity and buffering, while maximizing pipelining.
    Type: Application
    Filed: March 15, 2005
    Publication date: April 13, 2006
    Inventors: Franck Seigneret, Nabil Khalifa, Sivayya Ayinala, Praveen Kolli
  • Publication number: 20060080478
    Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.
    Type: Application
    Filed: March 17, 2005
    Publication date: April 13, 2006
    Inventors: Franck Seigneret, Sivayya Ayinala, Nabil Khalifa, Praveen Kolli, Prabha Atluri