Abstract: A system and method for performing tensor transforms on customized digital hardware. The system is comprised of a plurality of computational blocks, a control unit, and memory. The control unit is configured to read the generated source tensor slices for the generated indexes and read from memory the source tensor data and weight data interpolate the tensor slices based on the weights according to a transformation guide. The source tensor data and tensor weights are sent to multiple computational blocks for parallel generation of interpolated output tensor data. The data in memory can be configured so that only one address is needed to read multiple tensor dimensions or a tensor slice. Additionally, the memory can be configured to accept multiple memory addresses in parallel. The computational block output provides a grid-sampled output tensor.

Abstract: A power-efficient and clock-shaping clock structure for a digital semiconductor device. The device can include an array of logic blocks. A root-column clock trace is coupled to column-clock traces extending along each column of the array. The clock traces feed the logic block at evenly spaced points to control the delay time for the execution of the logic blocks. The root-column clock trace is fed a clock from a single endpoint that result in a propagation wave of logic blocks execution. The clock structure can include row-clock traces placed across the array rows and coupled to a root-row clock trace. Each logic block can receive a clock from the intersection of the column-clock trace and the row-clock trace. A clock input at a single point where the root-column clock trace and root-row clock trace meet.

Abstract: Artificial intelligence is an extremely computationally intensive field such that it can be expensive, time consuming, and energy consuming. Fortunately, many of the calculations required for artificial intelligence can be performed in parallel such that specialized processors can greatly increase computational performance. Specifically, artificial intelligence generally requires large numbers of matrix operations to implement neural networks such that specialized matrix processor circuits can improve performance. To perform all these matrix operations, the matrix processor circuits must be quickly and efficiently supplied with data to process or else the matrix processor circuits end up idle or spending large amounts of time loading in different weight matrix data.

Abstract: Artificial intelligence is an increasingly important sector of the computer industry. However, artificial intelligence is extremely computationally intensive field such that it can be expensive, time consuming, and energy consuming. Fortunately, many of the calculations required for artificial intelligence can be performed in parallel such that specialized processors can great increase computational performance. Specifically, artificial intelligence generally requires large numbers of matrix operations to implement neural networks such that specialized matrix processor circuits can improve performance. To perform all these matrix operations, the matrix processor circuits must be quickly and efficiently supplied with data to process or else the matrix processor circuits end up idle or spending large amounts of time loading in different weight matrix data.

Abstract: A traffic manager for a network switch port includes a buffer memory and a buffer manager for writing incoming cells into the buffer memory and for thereafter reading the cells out of the buffer memory and forwarding them. The traffic manager also includes a queue manager for determining an order in which the buffer manager is to forward a set of cells stored in the buffer memory. The queue manager supplies the buffer manager with a sequence of pointers, each pointer referencing a separate cell of the set of cells, with the sequence of pointers being ordered to indicate an order in which the buffer manager is to forward the set of cells. After receiving the pointer sequence, the buffer manager changes the order of pointers in the pointer sequence to optimize a rate at which it can read the cells out of the buffer memory.

Abstract: A traffic manager for a network switch port includes a buffer memory and a buffer manager for writing incoming cells into the buffer memory and for thereafter reading the cells out of the buffer memory and forwarding them. The traffic manager also includes a queue manager for determining an order in which the buffer manager is to forward a set of cells stored in the buffer memory. The queue manager supplies the buffer manager with a sequence of pointers, each pointer referencing a separate cell of the set of cells, with the sequence of pointers being ordered to indicate an order in which the buffer manager is to forward the set of cells. After receiving the pointer sequence, the buffer manager changes the order of pointers in the pointer sequence to optimize a rate at which it can read the cells out of the buffer memory.