Abstract: The present disclosure provides a resource allocation method and apparatus, a readable medium and an electronic device. The method includes: acquiring a target resource type corresponding to a target task; acquiring a plurality of resource types of a target processor, wherein each resource type corresponds to one or more virtual processor resources of the target processor; determining a specified resource type that is identical to the target resource type from the plurality of resource types; determining a target processor resource from one or more virtual processor resources corresponding to the specified resource type; and allocating the target processor resource to the target task.

Abstract: The present application provides a method and a device for designing a gate driving circuit, a controller, and a storage medium. The method includes: acquiring size information of a target panel and determining location information of a target area according to the size information of the target panel; calling and combining size information of a standard panel, characteristic label information of a plurality of standard devices, and an architecture type identifier acquired to determine characteristic label information of at least one target device, in order to generate a target gate driving circuit in the target area.

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

Abstract: In a design stage of post spacers of a display panel, the present application generates a post spacer array pattern that meets requirements of a user according to a drawing layer data, a ratio data, and a positioning mode data of each of types of the post spacers determined by the user. This realizes an intelligent design of the post spacers of the display panel and eliminates manual judgments and modifications, thereby increasing efficiency and accuracy of a design process of the post spacers of the display panel.

Abstract: A low-order vessel propulsion power prediction method may be performed to determine factors, including power demand parameters, used in configuring a propulsion system for a marine vessel. The low-order method may receive stability data and vessel operation profile data, in addition to computational fluid dynamics simulation results to determine predicted vessel power profiles. The predicted vessel power profiles may be used to configure a powertrain system model for the marine vessel.

Abstract: A remote reconfiguration system for an Internet of Things (IoT) intelligent sensing terminal includes: a controlled terminal with a field programmable gate array (FPGA); and a remote control unit connected to the controlled terminal and a control device; where the remote control unit is configured to receive control information sent by the control device, process the control information and send the processed control information to the FPGA, such that the FPGA performs remote local autonomous reconfiguration based on the preprocessed control information. The system resolves problems that a traditional IoT terminal cannot realize remote control and cannot follow functional requirements to perform local autonomous reconfiguration, and has better versatility and expandability.

Abstract: Provided is a method for determining a pregnancy status of a pregnant woman, including: (1) constructing a training set and a selective verification set, each of the training set and the selective verification set being composed of pregnant woman samples each having a known pregnancy status; (2) determining predetermined parameters of each pregnant woman sample in the training set, the predetermined parameters including a concentration of fetal cell-free nucleic acids in peripheral blood and a gestational age in week at which sampling for the peripheral blood is conducted; (3) constructing a prediction model based on the known pregnancy status and the predetermined parameters; (4) determining predetermined parameters of the pregnant woman; and (5) determining the pregnancy status of the pregnant woman based on the predetermined parameters and the constructed prediction model.

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.

Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region.

Abstract: The technology disclosed in this patent document can be used to implement an optical coherent tomography (OCT) system that combines a control of the probe light to the target sample with different optical aberration patterns in optically probing the target sample and an OCT imaging processing to enhance the OCT imaging quality by combining image signals from in-phase contributions from the probing with different optical aberration patterns while suppressing randomly phased contributions from scattering by the target sample.

Abstract: A highly-dispersed hydrogenation catalyst, a preparation method thereof, and use thereof in the preparation of biofuel from palm oil or other oil are provided. The combination of maleic anhydride-grafted polypropylene (MA-PP) and a silane coupling agent (SCA) is introduced into an aluminum oxide composite carrier through organic amidation to obtain a uniformly-dispersed composite carrier with regular pores. Moreover, through a multi-stage impregnation and roasting process, a particle size of an active component is greatly reduced, and the dispersion of the active component and the number of active sites are improved. A hydrogenation catalyst with high hydrothermal stability, high hydrogenation activity, and long life is prepared based on the composite carrier with regular pores and used in the preparation of biofuel from vegetable oil or other oil through hydrodeoxygenation (HDO), which has great industrial application value.

Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.

Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.

Abstract: A power semiconductor device includes a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.

Abstract: Provided is a base mutation detection method, which includes: determining an initial frequency of sequencing data of samples being a specific base at an interested locus; calculating, based on the initial frequency, an expected value of each sample being the specific base at the interested locus; updating the initial frequency of the sequencing data of the samples being the specific base at the interested locus; further calculating the expected value of each sample being the specific base at the interested locus, further updating the initial frequency of the sequencing data of the samples being the specific base at the interested locus, and repeating the foregoing iteration until the expected value of each sample being the specific base at the interested locus converges; and determining, based on each converging expected value, a base mutation type and a mutation confidence at the interested locus of each sample.

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.