Patents by Inventor Siyang Liu

Siyang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220223692
    Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.
    Type: Application
    Filed: September 25, 2020
    Publication date: July 14, 2022
    Applicants: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO.,LTD
    Inventors: SIYANG LIU, NINGBO LI, DEJIN WANG, KUI XIAO, CHI ZHANG, SHENG LI, XINYI TAO, WEIFENG SUN, LONGXING SHI
  • Patent number: 11322606
    Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 3, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Weifeng Sun, Siyang Liu, Sheng Li, Chi Zhang, Xinyi Tao, Ningbo Li, Longxing Shi
  • Publication number: 20220115532
    Abstract: A power semiconductor device includes a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 14, 2022
    Inventors: Weifeng SUN, Rongcheng LOU, Kui XIAO, Feng LIN, Jiaxing WEI, Sheng LI, Siyang LIU, Shengli LU, Longxing SHI
  • Publication number: 20220068437
    Abstract: Provided is a base mutation detection method, which includes: determining an initial frequency of sequencing data of samples being a specific base at an interested locus; calculating, based on the initial frequency, an expected value of each sample being the specific base at the interested locus; updating the initial frequency of the sequencing data of the samples being the specific base at the interested locus; further calculating the expected value of each sample being the specific base at the interested locus, further updating the initial frequency of the sequencing data of the samples being the specific base at the interested locus, and repeating the foregoing iteration until the expected value of each sample being the specific base at the interested locus converges; and determining, based on each converging expected value, a base mutation type and a mutation confidence at the interested locus of each sample.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Inventors: Siyang LIU, Shujia HUANG, Xin JIN
  • Publication number: 20220069115
    Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.
    Type: Application
    Filed: December 19, 2019
    Publication date: March 3, 2022
    Inventors: Siyang LIU, Chi ZHANG, Kui XIAO, Guipeng SUN, Dejin WANG, Jiaxing WEI, Li LU, Weifeng SUN, Shengli LU
  • Publication number: 20210336009
    Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.
    Type: Application
    Filed: September 25, 2018
    Publication date: October 28, 2021
    Applicant: SOUTHEAST UNIVERSITY
    Inventors: Weifeng SUN, Siyang LIU, Lizhi TANG, Sheng LI, Chi ZHANG, Jiaxing WEI, Shengli LU, Longxing SHI
  • Patent number: 11158708
    Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 26, 2021
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Weifeng Sun, Siyang Liu, Lizhi Tang, Sheng Li, Chi Zhang, Jiaxing Wei, Shengli Lu, Longxing Shi
  • Publication number: 20210234030
    Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.
    Type: Application
    Filed: October 21, 2019
    Publication date: July 29, 2021
    Inventors: Weifeng SUN, Siyang LIU, Sheng LI, Chi ZHANG, Xinyi TAO, Ningbo LI, Longxing SHI
  • Publication number: 20210118384
    Abstract: The invention provides a pixel driving circuit and LCD device. The pixel driving circuit electrically connects the drain of the third TFT of each sub-pixel in the N-th sub-pixel row to the first end of the second LC capacitor of a corresponding sub-pixel of the (N+1)th row. When driving, when scanning the N-th sub-pixel row, the third TFT of the N-th sub-pixel row turns on to release the voltage at the first end of the second LC capacitor of the N-th sub-pixel row to the first end of the second LC capacitor of the (N+1)th sub-pixel row, and does not affect the voltage on the array substrate common voltage line, thereby effectively ensuring consistent voltage value for various areas on the array substrate common voltage line. When applied to LCD device, the invention can improve the display quality of the LCD device.
    Type: Application
    Filed: September 26, 2018
    Publication date: April 22, 2021
    Inventor: Siyang Liu
  • Patent number: 10971094
    Abstract: The invention provides a pixel driving circuit and LCD device. The pixel driving circuit electrically connects the drain of the third TFT of each sub-pixel in the N-th sub-pixel row to the first end of the second LC capacitor of a corresponding sub-pixel of the (N+1)th row. When driving, when scanning the N-th sub-pixel row, the third TFT of the N-th sub-pixel row turns on to release the voltage at the first end of the second LC capacitor of the N-th sub-pixel row to the first end of the second LC capacitor of the (N+1)th sub-pixel row, and does not affect the voltage on the array substrate common voltage line, thereby effectively ensuring consistent voltage value for various areas on the array substrate common voltage line. When applied to LCD device, the invention can improve the display quality of the LCD device.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: April 6, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Siyang Liu
  • Publication number: 20210043079
    Abstract: The present disclosure discloses a vehicle information interacting method, device, apparatus, and a storage medium, and relates to the field of intelligent transportation. A specific implementation is: determining a first message according to an autonomous driving level of a vehicle, the first message carries information indicating the autonomous driving level of the vehicle and information indicating an autonomous driving status of the vehicle, and broadcasting the first message, so that other in-vehicle interaction apparatus or roadside apparatus within a communication range of the vehicle receives the first message. The autonomous driving level and the autonomous driving status of the vehicle are acquired by receiving the first message, realizing the sharing of information between vehicles and the monitoring of vehicle information by the roadside apparatus, and improving the safety of transportation environment and the traffic efficiency.
    Type: Application
    Filed: August 5, 2020
    Publication date: February 11, 2021
    Inventors: Siyang LIU, Xing HU, Shangyi CHEN
  • Publication number: 20210003382
    Abstract: The technology disclosed in this patent document can be used to implement an optical coherent tomography (OCT) system that combines a control of the probe light to the target sample with different optical aberration patterns in optically probing the target sample and an OCT imaging processing to enhance the OCT imaging quality by combining image signals from in-phase contributions from the probing with different optical aberration patterns while suppressing randomly phased contributions from scattering by the target sample.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Inventors: Steven Adie, Siyang Liu, Michael Lamont
  • Patent number: 10479944
    Abstract: A hydrodeoxygenation catalyst takes self-made porous large-specific surface nano-alumina as a carrier, takes NixMoW, NixCoW or NixCoMo as an active component, and takes Mn as an assistant. Hydrothermal stability of the catalyst and dispersion of active components may be increased by enlarging a pore channel and a specific surface area of the carrier, thereby prolonging the life of the hydrodeoxygenation catalyst. A hydroisomerization catalyst takes multi-walled carbon nanotube composite hierarchical-pore-channel NiAPO-11 or NiSAPO-11 as a carrier and takes NixMoLa, NixCoLa or NixWLa as an active component. Due to the adding of the carbon nanotubes, the pore channel of the carrier is enriched, and connection between the active components and the carrier is effectively enhanced, thereby prolonging the life of the catalyst on a basis of increasing selectivity of aviation kerosene component. Moreover, the biological aviation kerosene satisfying usage conditions is prepared by virtue of mild reaction conditions.
    Type: Grant
    Filed: November 18, 2017
    Date of Patent: November 19, 2019
    Inventors: Wei Li, SiYang Liu, Qingxin Guan, Bohan Chai, Liangnian He, Feng Ye, Xiaoying Cui
  • Patent number: 10378101
    Abstract: Disclosed is an apparatus for film formation by physical sputtering, which includes a vacuum chamber; a substrate platform arranged inside of the chamber, and provided thereon with a substrate to be formed with a film; a target material arranged inside of the chamber, and arranged opposite to the substrate; at least one square resistance meter, which is connected to the target material to real-timely measure an actual resistance value of the target material; an excitation source, which is used to bombard the target material for sputtering atoms of the target material; and a control system, which is connected to the square resistance meter. The apparatus for film formation by physical sputtering has a simple structure, can monitor the consumption of the target material in real time, effectively avoid damage of a backboard and abnormality of a product resulting from breakdown of the target material, and improve the quality of the product.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: August 13, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Siyang Liu
  • Patent number: 10340906
    Abstract: Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: July 2, 2019
    Assignees: SOUTHEAST UNIVERSITY, SOUTHEAST UNIVERSITY-WUXI INTEGRATED CIRCUIT TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Weifeng Sun, Yunwu Zhang, Kuo Yu, Jing Zhu, Shen Xu, Qinsong Qian, Siyang Liu, Shengli Lu, Longxing Shi
  • Patent number: 10288949
    Abstract: Provided is a liquid crystal display panel used in a curved display device and the curved display device. This belongs to the field of display technologies, and solves the technical problem of inferior display caused by inhomogeneous cell thickness that would easily occur to an existing curved display device. The liquid crystal display panel includes: an upper substrate provided with a plurality of spacers thereon; and a lower substrate provided with a plurality of bosses thereon, in one-to-one correspondence with the plurality of spacers. At least one of the plurality of spacers has a distance to a central axis of the liquid crystal display panel shorter than a distance from its corresponding boss to the central axis of the liquid crystal display panel. The liquid crystal display panel can be used in large-sized curved display devices such as liquid crystal display televisions.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: May 14, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Siyang Liu, Zui Wang
  • Publication number: 20190003038
    Abstract: Disclosed is an apparatus for film formation by physical sputtering, which includes a vacuum chamber; a substrate platform arranged inside of the chamber, and provided thereon with a substrate to be formed with a film; a target material arranged inside of the chamber, and arranged opposite to the substrate; at least one square resistance meter, which is connected to the target material to real-timely measure an actual resistance value of the target material; an excitation source, which is used to bombard the target material for sputtering atoms of the target material; and a control system, which is connected to the square resistance meter. The apparatus for film formation by physical sputtering has a simple structure, can monitor the consumption of the target material in real time, effectively avoid damage of a backboard and abnormality of a product resulting from breakdown of the target material, and improve the quality of the product.
    Type: Application
    Filed: May 25, 2017
    Publication date: January 3, 2019
    Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., L TD.
    Inventor: Siyang LIU
  • Publication number: 20180262186
    Abstract: Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.
    Type: Application
    Filed: January 23, 2017
    Publication date: September 13, 2018
    Inventors: Weifeng SUN, Yunwu ZHANG, Kuo YU, Jing ZHU, Shen XU, Qinsong QIAN, Siyang LIU, Shengli LU, Longxing SHI
  • Patent number: 10067384
    Abstract: A detection unit for lighting detection of an LCD, an array structure comprising the detection unit, a liquid crystal display comprising the the array structure, and a detection method for lighting detection of an LCD are provided. Processes of original RGB displays are improved, the shorting bars are reduced, and only one array mask is changed to implement the lighting detection of solid colors and mixed colors in semi-products of RGBW displays, and the production cost can be reduced.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: September 4, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Siyang Liu, Tienhao Chang
  • Patent number: 10056313
    Abstract: A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: August 21, 2018
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Siyang Liu, Ning Wang, Jiaxing Wei, Chao Liu, Weifeng Sun, Shengli Lu, Longxing Shi