Abstract: A conductive channel structure for SiC devices, a fully integrated SiC device and a fully integrated manufacturing process thereof are provided. The fully integrated SiC device features a low-voltage region, a first high-voltage region and a second high-voltage region separated by isolation structures on the same SiC-based chip, and integrates first and second conductivity type MOS devices. The first and second conductivity type devices employ first and second conductivity type conductive channels respectively with alternating N-type and P-type first or second conductivity type areas above them. The manufacturing process includes sequentially stacking a second conductivity type epitaxial layer and buffer layer on an N-type substrate; and within the second conductivity type buffer layer, arranging first conductivity type well regions, heavily doped regions, channel regions, second conductivity type well regions, isolation structures, heavily doped regions, and channel regions.

Abstract: A conductive channel structure for SiC devices, a fully integrated SiC device and a fully integrated manufacturing process thereof are provided. The fully integrated SiC device features a low-voltage region, a first high-voltage region and a second high-voltage region separated by isolation structures on the same SiC-based chip, and integrates first and second conductivity type MOS devices. The first and second conductivity type devices employ first and second conductivity type conductive channels respectively with alternating N-type and P-type first or second conductivity type areas above them. The manufacturing process includes sequentially stacking a second conductivity type epitaxial layer and buffer layer on an N-type substrate; and within the second conductivity type buffer layer, arranging first conductivity type well regions, heavily doped regions, channel regions, second conductivity type well regions, isolation structures, heavily doped regions, and channel regions.

Abstract: A horizontal Hall device includes a substrate layer and a BOX layer arranged on the substrate layer, where an epitaxial layer is arranged on the BOX layer, a well layer is arranged on the epitaxial layer, an STI layer is arranged on the well layer, a pair of induction electrodes and a pair of bias electrodes are arranged on the STI layer, ground electrodes are arranged on the epitaxial layer, and current barrier layers are arranged between the induction electrodes and the adjacent bias electrodes.

Abstract: A data processing method and apparatus including obtaining baseline performance information of a road side sensing device, the baseline performance information representing a sensing capability of the road side sensing device, and the road side sensing device being located in a road side area covered by the road side communication device, obtaining road side sensing data generated by the road side sensing device, and transmitting the road side sensing data and the baseline performance information to an on board terminal located in the road side area such that the on board terminal adjusts the road side sensing data based on the baseline performance information.

Abstract: A highly-dispersed hydrogenation catalyst, a preparation method thereof, and use thereof in the preparation of biofuel from palm oil or other oil are provided. The combination of maleic anhydride-grafted polypropylene (MA-PP) and a silane coupling agent (SCA) is introduced into an aluminum oxide composite carrier through organic amidation to obtain a uniformly-dispersed composite carrier with regular pores. Moreover, through a multi-stage impregnation and roasting process, a particle size of an active component is greatly reduced, and the dispersion of the active component and the number of active sites are improved. A hydrogenation catalyst with high hydrothermal stability, high hydrogenation activity, and long life is prepared based on the composite carrier with regular pores and used in the preparation of biofuel from vegetable oil or other oil through hydrodeoxygenation (HDO), which has great industrial application value.

Abstract: Provided is a base mutation detection method, which includes: determining an initial frequency of sequencing data of samples being a specific base at an interested locus; calculating, based on the initial frequency, an expected value of each sample being the specific base at the interested locus; updating the initial frequency of the sequencing data of the samples being the specific base at the interested locus; further calculating the expected value of each sample being the specific base at the interested locus, further updating the initial frequency of the sequencing data of the samples being the specific base at the interested locus, and repeating the foregoing iteration until the expected value of each sample being the specific base at the interested locus converges; and determining, based on each converging expected value, a base mutation type and a mutation confidence at the interested locus of each sample.

Abstract: A manufacturing method for a P-type laterally diffused metal oxide semiconductor device includes: forming a N-type buried layer in a substrate, forming a P-type region located on the N-type buried layer, and forming a mask layer located on the P-type region; patterning the mask layer to form at least two injection windows; performing N-type ion implantation by the at least two injection windows; forming an oxide layer; removing the mask layer; performing P-type ion implantation on the P-type region to form a P-type doped region; diffusing the P-type doped region to form a drift region and two P-type well regions, diffusing the high-voltage N-well doped region to form a high-voltage N-type well region, and diffusing the low-voltage N-well doped region to form a low-voltage N-type well region; and forming a source doped region, a drain doped region, and a gate.

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

Abstract: A power semiconductor device includes: a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.

Abstract: Embodiments of the present disclosure disclose a traffic control method and apparatus, a device, and a storage medium. The method includes: receiving a vehicle intention and request message transmitted by a vehicle, the vehicle intention and request message including signal priority request information, and the signal priority request information including at least one of classification information and load information of the vehicle; and transmitting target signal priority request information in the vehicle intention and request message to a road traffic signal control system, the target signal priority request information including at least one of the classification information and the load information of the vehicle. The target signal priority request information is configured for instructing the road traffic signal control system to determine, based on the target signal priority request information, whether to allow for priority passage of the vehicle at a first intersection.

Abstract: Embodiments of this application disclose a traffic control method and apparatus, a device, and a storage medium, and relate to the field of computer technologies. The method includes: generating a first signal priority request packet, the first signal priority request packet including N signal priority requests; transmitting the first signal priority request packet; and receiving a first signal priority response packet returned for the first signal priority request packet, the first signal priority response packet including N signal priority responses for the N signal priority requests, and the N signal priority responses including information configured for indicating a first road traffic signal control machine of a first intersection to control a traffic management and control device of the first intersection.

Abstract: In a design stage of post spacers of a display panel, the present application generates a post spacer array pattern that meets requirements of a user according to a drawing layer data, a ratio data, and a positioning mode data of each of types of the post spacers determined by the user. This realizes an intelligent design of the post spacers of the display panel and eliminates manual judgments and modifications, thereby increasing efficiency and accuracy of a design process of the post spacers of the display panel.

Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region.

Abstract: An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

Abstract: An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

Abstract: In the monolithically integrated GaN-based half-bridge circuit, a nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially provided on a conductive substrate, the barrier layer and the channel layer are separated by isolation layers, and a diode, an integrated capacitor, a low-side transistor, a high-side transistor, a first integrated resistor and a second integrated resistor are provided. The half-bridge circuit includes: a low-side transistor and a high-side transistor, wherein a drain of the low-side transistor is connected to a source of the high-side transistor and also connected to an output terminal Vout, and a substrate of the low-side transistor is connected to a substrate of the high-side transistor, wherein a series resistor is connected in parallel to a drain of the high-side transistor and a source of the low-side transistor.

Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

Abstract: A GaN power semiconductor device integrated with a self-feedback gate control structure comprises a substrate, a buffer layer, a channel layer and a barrier layer. A gate control area is formed by a first metal source electrode, a first P-type GaN cap layer, a first metal gate electrode, a first metal drain electrode, a second P-type GaN cap layer and a second metal gate electrode. An active working area is formed by the first metal source electrode, a third P-type GaN cap layer, a third metal gate electrode, a second metal drain electrode, the second P-type GaN cap layer and a second metal source electrode. The overall gate leaking current of the device is regulated by the gate control area, the integration level is high, the parasitic effect is small, and the charge-storage effect can be effectively relieved, thus improving the threshold stability of the device.

Abstract: An automatic conversion method and system of binding pins are provided. The automatic conversion method includes: defining signal identifiers of binding pins of a display panel; and recognizing the signal identifiers of the binding pins of the display panel automatically by an electronic design automation program, and generating and outputting signal identifiers of binding pins of a circuit board.

Abstract: The present application provides a method and a device for designing a pixel circuit, a controller, and a storage medium. The method includes: calling size information of a standard panel and characteristic label information of a plurality of standard devices, and combining with an architecture type identifier acquired to determine characteristic label information of at least one target device, in order to further determine a target pixel circuit to generate a target pixel circuit matrix comprising a plurality of the target pixel circuits.